HB52R329E22-F Datasheet, PDF (42/66 Pages) Elpida Memory – 256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM

HB52R329E22-F
Write command to Write command interval:
1. Same bank, same ROW address: When another write command is executed at the same ROW address of
the same bank as the preceding write command, the second write can be performed after an interval of no less
than 1 clock. In the case of burst writes, the second write command has priority.
WRITE to WRITE Command Interval (same ROW address in same bank)
CK
Command _ACTV
Address
Row
WRIT WRIT
Column A Column B
BA
Din
in A0 in B0 in B1 in B2 in B3
Bank0
Active
Column =A Column =B
Write
Write
Burst Write Mode
Burst Length = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two write commands with a precharge command and a
bank-active command.
3. Different bank: When the bank changes, the second write can be performed after an interval of no less than
1 clock, provided that the other bank is in the bank-active state. In the case of burst write, the second write
command has priority.
WRITE to WRITE Command Interval (different bank)
CK
Command _ACTV
Address
Row 0
BA
Din
Bank0
Active
ACTV WRIT WRIT
Row 1 Column A Column B
in A0 in B0 in B1 in B2 in B3
Bank3 Bank0 Bank3
Active Write Write
Burst Write Mode
Burst Length = 4
Data Sheet No. E0112H10
42