HB52R329E22-F Datasheet, PDF (35/66 Pages) Elpida Memory – 256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM

HB52R329E22-F
Operation of the Registered SDRAM module
Read/Write Operations
Bank active: Before executing a read or write operation, the corresponding bank and the row address must be
activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according to the
status of the Bank select address (BA) pin, and the row address (AX0 to AX11) is activated by the A0 to A11
pins at the bank active command cycle. An interval of t_RCD is required between the bank active command input
and the following read/write command input.
Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in the
(CE Latency - 1) cycle after read command set. The SDRAM module can perform a burst read operation.
The burst length can be set to 1, 2, 4, 8 or full-page. The start address for a burst read is specified by the column
address and the bank select address (BA) at the read command set cycle. In a read operation, data output starts
after the number of clocks specified by the CE Latency. The CE Latency can be set to 3 or 4.
When the burst length is 1, 2, 4 or 8, the Dout buffer automatically becomes High-Z at the next clock after the
successive burst-length data has been output.
The CE latency and burst length must be specified at the mode register.
CE Latency
CK
Command
Address
t _RCD
ACTV
READ
Row
Column
Dout
CL = 3
CL = 4
out 0 out 1 out 2 out 3
out 0 out 1 out 2 out 3
CL = CE latency
Burst Length = 4
Data Sheet No. E0112H10
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