HB52R329E22-F Datasheet, PDF (41/66 Pages) Elpida Memory – 256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM

HB52R329E22-F
Command Intervals
Read command to Read command interval:
1. Same bank, same ROW address: When another read command is executed at the same ROW address of
the same bank as the preceding read command execution, the second read can be performed after an interval of
no less than 1 clock. Even when the first command is a burst read that is not yet finished, the data read by the
second command will be valid.
READ to READ Command Interval (same ROW address in same bank)
CK
Command
ACTV
Address
Row
BA
READ READ
Column A Column B
Dout
Bank0
Active
Column =A Column =B
Read
Read
out A0 out B0 out B1 out B2 out B3
Column =A Column =B
Dout
Dout
CE Latency = 4
Burst Length = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read
commands cannot be executed; it is necessary to separate the two read commands with a precharge command
and a bank-active command.
3. Different bank: When the bank changes, the second read can be performed after an interval of no less than
1 clock, provided that the other bank is in the bank-active state. Even when the first command is a burst read
that is not yet finished, the data read by the second command will be valid.
READ to READ Command Interval (different bank)
CK
Command
Address
BA
ACTV
Row 0
Dout
Bank0
Active
ACTV READ READ
Row 1 Column A Column B
Bank3 Bank0 Bank3
Active Read Read
out A0 out B0 out B1 out B2 out B3
Bank0 Bank3
Dout Dout
CE Latency = 4
Burst Length = 4
Data Sheet No. E0112H10
41