HB52R329E22-F Datasheet, PDF(52/66 Page) Elpida Memory – 256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM

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HB52R329E22-F Datasheet, PDF (52/66 Pages) Elpida Memory – 256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM

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HB52R329E22-F

Mode register set to Bank-active command interval: The interval between setting the mode register and

executing a bank-active command must be no less than lRSA.

Command

MRS

ACTV

Address

CODE BS & ROW

I RSA

Mode

Bank

DQMB Control

The DQMB mask the DQ data. The timing of DQMB is different during reading and writing.

Reading: When data is read, the output buffer can be controlled by DQMB. By setting DQMB to Low, the

output buffer becomes Low-Z, enabling data output. By setting DQMB to High, the output buffer becomes

High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency

of DQMB during reading is 3 clocks.

Writing: Input data can be masked by DQMB. By setting DQMB to Low, data can be written. In addition,

when DQMB is set to High, the corresponding data is not written, and the previous data is held. The latency of

DQMB during writing is 1 clock.

Data Sheet No. E0112H10

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