HB52R329E22-F Datasheet, PDF (16/66 Pages) Elpida Memory – 256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM

HB52R329E22-F
DC Characteristics (Ta = 0 to 55°C, V_CC = 3.3 V ± 0.3 V, V_SS = 0 V)
HB52R329E22
-A6F/B6F
Parameter
Symbol Min
Max
Unit Test conditions
Notes
Operating current
(CE latency = 3)
I _CC1
—
(CE latency = 4)
I _CC1
—
Standby current in power down I_CC2P
—
Standby current in power down I_CC2PS
—
(input signal stable)
2315
2315
803
767
Burst length = 1
mA
t_RC = min
mA
1, 2, 3
mA
CKE = V_IL, t_CK = 12 ns 6
mA
CKE = V_IL, t_CK = ∞
7
Standby current in non power I_CC2N
—
down
Active standby current in power I_CC3P
—
down
1271
839
mA
CKE, S = V_IH,
4
t_CK = 12 ns
mA
CKE = V_IL, t_CK = 12 ns 1, 2, 6
Active standby current in non I_CC3N
—
power down
Burst operating current
(CE latency = 3)
(CE latency = 4)
Refresh current
Self refresh current
I _CC4
—
I _CC4
—
I _CC5
—
I _CC6
—
Input leakage current
Output leakage current
I _LI
–10
I _LO
–10
1415
2315
2315
3125
731
10
10
mA
CKE, S = V_IH,
t_CK = 12 ns
t_CK = min, BL = 4
mA
mA
mA
t_RC = min
mA
V_IH ≥ V_CC – 0.2 V
V_IL ≤ 0.2 V
µA
0 ≤ Vin ≤ V_CC
µA
0 ≤ Vout ≤ V_CC
DQ = disable
1, 2, 4
1, 2, 5
3
8
Output high voltage
V_OH
2.4
—
V
I_OH = –4 mA
Output low voltage
V_OL
—
0.4
V
I_OL = 4 mA
Notes: 1. I_CC depends on output load condition when the device is selected. I_CC (max) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CK operating current.
7. After power down mode, no CK operating current.
8. After self refresh mode set, self refresh current.
Data Sheet No. E0112H10
16