HB52R329E22-F Datasheet, PDF (48/66 Pages) Elpida Memory – 256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM

HB52R329E22-F
Read command to Precharge command interval (same bank):
When the precharge command is executed for the same bank as the read command that preceded it, the minimum
interval between the two commands is one clock. However, since the output buffer then becomes High-Z after
the clocks defined by l_HZP, there is a case of interruption to burst read data output will be interrupted, if the
precharge command is input during burst read. To read all data by burst read, the clocks defined by l_EP must be
assured as an interval from the final data output to precharge command execution.
READ to PRECHARGE Command Interval (same bank): To output all data
CE Latency = 3, Burst Length = 4
CK
Command
READ
Dout
CL=3
CE Latency = 4, Burst Length = 4
PRE/PALL
out A0 out A1 out A2 out A3
l EP = -2 cycle
CK
Command
Dout
READ
CL=4
PRE/PALL
out A0 out A1 out A2 out A3
l EP = -3 cycle
Data Sheet No. E0112H10
48