HB52R329E22-F Datasheet, PDF (36/66 Pages) Elpida Memory – 256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM

HB52R329E22-F
Burst Length
CK
Command
t _RCD
ACTV
READ
Address
Row
Column
Dout
BL = 1
BL = 2
BL = 4
BL = 8
BL = full page
out 0
out 0 out 1
out 0 out 1 out 2 out 3
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 8
out 0-1 out 0 out 1
BL : Burst Length
CE Latency = 3
Write operation: Burst write or single write mode is selected by the OPCODE (A13, A12, A11, A10, A9, A8)
of the mode register.
1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts
in the next clock as a write command set. (The latency of data input is 1 clock.) The burst length can be set to
1, 2, 4, 8, and full-page, like burst read operations. The write start address is specified by the column address
(and the bank select address (BA) at the write command set cycle.
CK
Command
t _RCD
ACTV
WRIT
Address
Row
Column
BL = 1
BL = 2
Din
BL = 4
BL = 8
BL = full page
in 0
in 0 in 1
in 0 in 1 in 2 in 3
in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7
in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7 in 8
in 0-1 in 0 in 1
CE Latency = 3, 4
Data Sheet No. E0112H10
36