HB52R329E22-F Datasheet, PDF(25/66 Page) Elpida Memory – 256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM

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HB52R329E22-F Datasheet, PDF (25/66 Pages) Elpida Memory – 256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM

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HB52R329E22-F

DQMB Truth Table

Command

Write enable/output enable

Write inhibit/output disable

Note:

H: VIH. L: VIL. Ã: VIH or VIL.

Write: IDID is needed.

Read: IDOD is needed.

CKE

Symbol

n-1

ENB

MASK

DQMB

The SDRAM module can mask input/output data by means of DQMB.

During reading, the output buffer is set to Low-Z by setting DQMB to Low, enabling data output. On the other

hand, when DQMB is set to High, the output buffer becomes High-Z, disabling data output.

During writing, data is written by setting DQMB to Low. When DQMB is set to High, the previous data is held

(the new data is not written). Desired data can be masked during burst read or burst write by setting DQMB.

For details, refer to the DQMB control section of the SDRAM module operating instructions.

CKE Truth Table

CKE

Current state

Command

n-1 n

RE CE W Address

Active

Clock suspend mode entry

Any

Clock suspend

Clock suspend Clock suspend mode exit

Idle

Auto-refresh command (REF)

Idle

Self-refresh entry (SELF)

Idle

Power down entry

Self refresh

Self refresh exit (SELFX)

Power down

Power down exit

Note: H: VIH. L: VIL. Ã: VIH or VIL.

Clock suspend mode entry: The SDRAM module enters clock suspend mode from active mode by setting

CKE to Low. If command is input in the clock suspend mode entry cycle, the command is valid. The clock

suspend mode changes depending on the current status (1 clock before) as shown below.

Data Sheet No. E0112H10

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