STC5230_15 Datasheet, PDF (7/64 Pages) Connor-Winfield Corporation – Line Card Clock

STC5230
Synchronous Clock for SETS
Data Sheet
Table 1: Pin Description
Pin Name
Pin #
I/O
Description
REF11
REF12
21
I Reference input 11
23
I Reference input 12
T0_M/S
24
I Select master or slave mode for T0, 1: Master, 0: Slave
T0_XSYNC_IN
25
I
Cross-couple SyncLink^TM data link input for T0 for master/slave redundant applications
T0_XSYNC_OUT
70
O _{Cross-couple SyncLink}^TM _{data link output for T0 for master/slave redundant applications}
CLK0_P
62
O^{1 155.52/125 MHz LVPECL output (T0) or 1MHz to 156.25MHz, in 1kHz steps}
CLK0_N
63
O^{1 155.52/125 MHz LVPECL output (T0) or 1MHz to 156.25MHz, in 1kHz steps}
CLK1
83
O 19.44/38.88/51.84/77.76/25/50/125MHz (T0) or 1MHz to 156.25MHz, in 1kHz steps
CLK2
81
O 19.44/38.88/51.84/77.76/25/50/125MHz (T0) or 1MHz to 156.25MHz, in 1kHz steps
CLK3
CLK4
CLK5
79
O 8 kHz frame pulse or 50% duty cycle clock (T0)
77
O 2 kHz frame pulse or 50% duty cycle clock (T0)
74
O 44.736/34.368 MHz (T0) or 1MHz to 156.25MHz, in 1kHz steps
CLK6
CLK7
72
O 1.544/3.088/6.176/12.352/24.704/2.048/4.098/8.192/16.384/32.768 MHz (T0) or 1MHz to
156.25MHz, in 1kHz steps
68
O 1.544/2.048 MHz (T4) or 1MHz to 156.25MHz, in 1kHz steps
CLK8_P
85
O^{1 125 MHz LVPECL output (T0) or 1MHz to 156.25MHz, in 1kHz steps}
CLK8_N
86
O^{1 125 MHz LVPECL output (T0) or 1MHz to 156.25MHz, in 1kHz steps}
LM0
LM1
Test_Pin
96
7
11,49
I Hardware and firmware configuration data mode pin 0
I Hardware and firmware configuration data mode pin 1
I Test pins, must be grounded for normal operation
NC
1, 9, 18,
Pins may be connected to ground(0V) up to Vdd, or floating
26, 27,
28,38,
39,40,42,
43, 47,
48,52,
53,
54,55,57,
58, 60,
65, 66,
73, 75,
76, 84,
92, 98,
100
Note 1: CLK0 and CLK8 are LVPECL
Page 7 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011