STC5230_15 Datasheet, PDF (1/64 Pages) Connor-Winfield Corporation – Line Card Clock

STC5230
Synchronous Clock for SETS
Data Sheet
Description
Features
Functional Specification
The RoHS 6/6 compliant STC5230 is a single chip
solution for the timing source in SDH, SONET, and
Synchronous Ethernet network elements. The device is
fully compliant with ITU-T G.813, G.8262, Telcordia
GR1244, and GR253.
- Suitable for SDH SETS, SONET Stratum 3, 4E, 4 and
SMC, and Synchronous Ethernet
- Two timing generators, T0 and T4, for SETS
- Complies with ITU-T G.813 opt1/2, G.8262 EEC opt1/2,
Telcordia GR1244 and GR253
The STC5230 accepts 12 reference inputs and gener-
ates 9 independent synchronized output clocks. Refer-
ence inputs are individually monitored for activity and
quality. Reference selection may be automatic, manual, and
hard-wired manual. Active reference selection may be
manual or automatic. All reference switches are hitless.
Synchronized outputs may be programmed for some
certain SONET and SDH as well as Synchronous Ether-
net frequencies or wide variety of frequencies from
1MHz up to 156.25MHz, in 1kHz steps.
Two independent timing generators, T0 and T4, provide
the essential functions for Synchronous Equipment Tim-
ing Source (SETS). Each timing generator includes a
DPLL (Digital Phase-Locked Loop), which may operate
in the Freerun, Synchronized, and Holdover modes.
Timing generator T0 supports master/slave operation for
redundant applications. The proprietary SyncLink^TM
cross-couple data link provides master/slave phase
information and state data to ensure seamless side
switches.
- Supports Master/Slave for redundant application with the
SyncLink^TM cross-couple data links
- Supports 4 different frequencies of external oscillator
(programmable): 10MHz, 12.8MHz, 19.2MHz, 20MHz
- Accepts 12 individual clock reference inputs
- Supports automatically frequency detection or manually
acceptable frequency. Each reference input is monitored
for activity and quality
- Supports manual and automatic reference selection
- 9 synchronized output clocks
- T0 and T4 have independent reference lists and priority
tables for automatic reference selection
- Provides compensation for the phase delay of the mas-
ter/slave cross-couple links, in 0.1ns steps up to 409.5ns
- Provides measurement of the round-trip phase delay of
the master/slave cross-couple links.
- Phase align locking and hit-less reference switching
- Phase rebuild on re-lock and reference switches
- Programmable loop bandwidth (T0/T4) 0.1Hz to 103Hz
A standard SPI serial bus interface provides access to
the STC5230’s comprehensive, yet simple to use inter-
nal control and status registers. The device operates
with an external OCXO or TCXO.
The STC5230 may be field upgraded with an optional
external EEPROM or via the bus interface.
- Supports SPI bus interface
- Field upgrade capability
- IEEE 1149.1 JTAG boundary scan
- Available in TQFP100 package
T0_MASTER_SLAVE
T0_XSYNC_IN
Phase
Detector
Digital
Filter
CLK0 LVPECL
CLK1
CLK2
12
Reference Clk
T0 Active
Ref Selector
Activity &
Frequency
Offset Monitor
T4 Active
Ref Selector
STC5230
T0
Clock
Synthesizers
CLK3 (8kHz)
CLK4 (2kHz)
CLK5
CLK6
CLK8 LVPECL
T0_XSYNC_OUT
Phase
Detector
Digital
Filter
T4
Clock
Synthesizer
CLK7
OCXO
TCXO
Serial Bus
Interface
Control & Status
Registers
IEEE 1194.1
JTAG
Figure 1: Functional Block Diagram
Page 1 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011