STC5230_15 Datasheet, PDF (28/64 Pages) Connor-Winfield Corporation – Line Card Clock

STC5230
Synchronous Clock for SETS
Data Sheet
Processor Interface Descriptions
The STC5230 supports the serial SPI bus interface. The description of the SPI bus’s interface timing is
following:
The SPI interface bus mode uses the SPI_CS, SPI_SCK, SPI_SDI, and SPI_SDO pins, corresponding to CS,
SCLK, SDI, and SDO below respectively, with timing as shown in Figure 10 and Figure 11:
Serial Bus Timing
CS
t_CS
1
2
3
4
5
6
7
8
9
t_CSHLD
t_CSMIN
10 11 12 13 14 15 16
t_CSTRI
SCLK
t_Ds
t_Dh
t_CH
t_CL
SDI
SDO
A6 A5 A4 A3 A2 A1 A0 1
MSB
LSB
t_DRDY
t_DHLD
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
Figure 10: Serial Bus Timing, Read access
CS
t_CS
t_CSHLD
t_CSMIN
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SCLK
t_Ds
t_Dh
t_CH
t_CL
SDI
A6 A5 A4 A3 A2 A1 A0 0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
MSB
LSB
Figure 11: Serial Bus Timing, Write access
Page 28 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011