STC5230_15 Datasheet, PDF (61/64 Pages) Connor-Winfield Corporation – Line Card Clock

STC5230
Synchronous Clock for SETS
Data Sheet
Revision History
The following table summarizes significant changes made in each revision. Additions reference current pages.
Revision
P01
P02
1.0
Change Description
Pages
Initial issue
Pin reassignment of CLK0_(P/N) and CLK8_(P/N)
Remove the 155.52MHz output feature from CLK8
Remove the phase align mode feature from Synchronization/Master mode
Add 62.5MHz selection on CLK1 and CLK2
4, 6
1, 6, 10, 17,
40
9, 13, 28, 32
1, 6, 17, 37
Add maximal value of Tj (operational junction temperature)
Bring back the Phase Align Mode back to Master/Synchronized operational
mode
Bring back the Phase Align Mode bit back to register T(0/4)_Control_Mode
Redefine the Phase Align Mode
Change the long term history accumulation filter (order, bandwidth list, and
default bandwidth)
Change the short term history accumulation filter (order, bandwidth list, and
default bandwidth)
Remove CLK0 from the phase alignment with other clock outputs
Change the loop bandwidth
Change the Transfer Attenuation Function
Change the description of the pull-in process
Remove CLK0 and CLK8 from the title of Figure 8
Correct T3 to DS3 in figure 6
7
9, 13, 28, 32
9, 13, 28, 32
13
14, 30, 34
14, 30, 34
18
1, 12, 28, 32,
43
43
13
18
17
Remove CLK0 and 8 from phase aligned to other T0 clock outputs
18
Page 61 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011