STC5230_15 Datasheet, PDF (44/64 Pages) Connor-Winfield Corporation – Line Card Clock

T4_Accu_Flush, 0x55 (W)
STC5230
Synchronous Clock for SETS
Data Sheet
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x55
Not used
HO flush
Writing to this register will perform a flush of the accumulated history. The value of bit HO flush determines
which histories are flushed.
HO flush Device Holdover History Tracking
0 = Flush and reset T4 long term history only
1 = Flush/reset both T4 long term history and the T4 device holdover history
CLK0_Sel, 0x56 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x56
Not used
CLK0 Select
Selects frequency of CLK0 or put CLK0 in tri-state in Freq Pre Defined mode. Freq Pre Defined mode (default
mode) of CLK0 is enabled by setting the register CLK_Index_Select to CLK0 and the register
CLK_User_Defined_Freq to 0.
Default value: 0
CLK1_Sel, 0x57 (R/W)
0x56, bits 1 ~ 0
0
1
2
3
CLK0 output
Tri-state
155.52MHz
125MHz
Reserved
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x57
Not used
CLK1 Select
Selects frequency of CLK1 or put CLK1 in tri-state in Freq Pre Defined mode. Freq Pre Defined mode (default
mode) of CLK1 is enabled by setting the register CLK_Index_Select to CLK1 and the register
CLK_User_Defined_Freq to 0.
0x57, bits 3 ~ 0
0
1
2
3
4
5
6
7
CLK1 output
Tri-state
19.44MHz
38.88MHz
77.76MHz
51.84MHz
25MHz
50MHz
125MHz
Page 44 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011