STC5230_15 Datasheet, PDF (32/64 Pages) Connor-Winfield Corporation – Line Card Clock

Default value: 20
Assert_Threshold, 0x0c (R/W)
STC5230
Synchronous Clock for SETS
Data Sheet
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x0c
Not used
Leaky bucket alarm assert threshold, 1 ~ 63
Sets the leaky bucket alarm assert threshold for the reference activity monitor. The alarm assert threshold
value must be greater than the de-assert threshold value and less than or equal to the bucket size value.
Invalid values will not be written to the register.
Default value: 15
De_Assert_Threshold, 0x0d (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x0d
Not used
Leaky bucket alarm de-assert threshold, 0 ~ 62
Sets the leaky bucket alarm de-assert threshold for the reference activity monitor. The de-assert threshold
value must be less than the assert threshold value. Invalid values will not be written to the register.
Default value: 10
Freerun_Cal, 0x0e (R/W)
Address
Bit7
0x0e
0x0f
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Lower 8 bits of freerun calibration
Not used
Upper 3 bits of freerun calibration
Freerun calibration, from -102.4 to +102.3 ppm, in 0.1ppm steps, two’s complement.
Default value: 0
Disqualification_Range, 0x10 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x10
Lower 8 bits of disqualification range
0x11
Not used
Upper 2 bits of disqualification range
Reference disqualification range, from 0 to +102.3 ppm, in 0.1 ppm steps. This also sets the pull-in range.
(See the Reference Input Monitoring and Qualification section)
Default value: 110 (range = 11.0 ppm).
Qualification_Range, 0x12 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x12
Lower 8 bits of qualification range
Page 32 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011