STC5230_15 Datasheet, PDF (45/64 Pages) Connor-Winfield Corporation – Line Card Clock

Default value: 1 (19.44MHz)
CLK2_Sel, 0x58 (R/W)
STC5230
Synchronous Clock for SETS
Data Sheet
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x58
Not used
CLK2 Select
Selects frequency of CLK2 or put CLK2 in tri-state in Freq Pre Defined mode. Freq Pre Defined mode (default
mode) of CLK2 is enabled by setting the register CLK_Index_Select to CLK2 and the register
CLK_User_Defined_Freq to 0.
0x58, bits 3 ~ 0
0
1
2
3
4
5
6
7
CLK2 output
Tri-state
19.44MHz
38.88MHz
77.76MHz
51.84MHz
25MHz
50MHz
125MHz
Default value: 2 (38.88MHz)
CLK3_Sel, 0x59 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x59
Not used
CLK3 Select
Selects pulse width of CLK3 (8KHz) or put CLK3 in tri-state. In variable pulse width, the width may be selected
from 1 to 62 times the period of the 155.52MHz output (~6.43ns to 399ns).
Default value: 63
CLK4_Sel, 0x5a (R/W)
0x59, bits 5 ~ 0
0
1 ~ 62
63
CLK3 (8kHz) output
Tri-state
Pulse width 1 to 62 cycles of 155.52MHz
50% duty cycle
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x5a
Not used
CLK4 Select
Selects pulse width of CLK4 (2kHz) or put CLK4 in tri-state. In variable pulse width, the width may be selected
from 1 to 62 times the period of the 155.52MHz output (~6.43ns to 399ns).
Page 45 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011