STC5230_15 Datasheet, PDF (48/64 Pages) Connor-Winfield Corporation – Line Card Clock

STC5230
Synchronous Clock for SETS
Data Sheet
Default value: 0
T0_MS_PHE, 0x62 (R)
Address
Bit7
0x62
0x63
0x64
Bit6
Bit5
Not used
Bit4
Bit3
Bit2
Bit1
Bit0
Bits 0 - 7 of 20 bit Phase Delay
Bits 8 - 15 of 20 bit Phase Delay
Bits 16 - 19 of 20 bit Phase Delay
T0’s phase delay of the round-trip cross-couple links from the master to the slave then back to the master. 2’s
complement. Resolution is (12.5ns/64 ~= 0.2ns). Range from (-125us/2) to (+125us/2). This value is valid only
when T0 is configured as in master mode.
CLK8_Sel, 0x65 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x65
Not used
CLK8 Select
Selects frequency of CLK8 or put CLK8 in tri-state in Freq Pre Defined mode. Freq Pre Defined mode (default
mode) of CLK8 is enabled by setting the register CLK_Index_Select to CLK8 and the register
CLK_User_Defined_Freq to 0.
Default value: 0
CLK_Index_Select, 0x66 (R/W)
0x65, bits 1 ~ 0
0
1
2
3
CLK8 output
Tri-state
125MHz
Reserved
Reserved
Address
Bit7
0x66
Bit6
Bit5
Not Used
Bit4
Bit3
Bit2
Bit1
Bit0
Clock index selection for clock output frequency in Freq
User Defined mode and phase skew adjustment
Determine which clock output is selected to program frequency in Freq User Defined mode at the register
CLK_User_Defined_Freq or which clock output is adjusted phase skew at the register CLK_Skew_Adj.
Field Value
0
1
2
3
4
5
6
Clock output
CLK0
CLK1
CLK2
Reserved
CLK5
CLK6
Page 48 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011