STC5230_15 Datasheet, PDF (15/64 Pages) Connor-Winfield Corporation – Line Card Clock

STC5230
Synchronous Clock for SETS
Data Sheet
General Description
The STC5230 is an integrated single chip solution for
the synchronous clock in SDH (SETS), SONET, and
Synchronous Ethernet network elements. Its highly
integrated design implements all of the necessary ref-
erence selection, monitoring, filtering, synthesis, and
control functions. An external OCXO or TCXO com-
pletes a system level solution (see Functional Block
Diagram, Figure 1). The device supports four pro-
grammable different frequencies of master clock:
10MHz, 12.8MHz, 19.2MHz, and 20MHz. Initial
default accepted frequency is 20MHz.
The STC5230 includes two timing generators, T0 and
T4, to implement the essential Synchronous Equip-
ment Timing Source (SETS) functions. Each timing
generator may be in either external-timing or self-tim-
ing mode. In external timing mode, a timing generator
may individually select one of the external reference
inputs as its active reference of its individual Digital
Phase-Locked Loop (DPLL). In self-timing mode, the
clock outputs are synthesized from the local oscillator
(the external TCXO/OCXO). T0 provides 8 of the
chip’s 9 clock outputs while T4 provides one clock
output. Additionally, T0 provides a cross reference
output for master/slave applications.
Each timing generator can individually operate in
Freerun, Synchronized, and Holdover mode. In
synchronized mode, the DPLL phase-locks to the
selected external reference. Phase lock may be set
as arbitrary or zero phase offset between the active
reference and clock outputs. Each DPLL’s loop band-
width may be programmed individually to vary the
DPLL’s filtering function. Conversely, both freerun
and holdover modes are self-timing. In freerun mode,
the clock outputs are synthesized and calibrated from
the local oscillator. In holdover mode, the clock
outputs are synthesized with a given frequency offset.
This frequency offset may be either a frequency
history previously accumulated by STC5230, or a
user supplied frequency offset. The stability of freerun
and holdover is simply determined by the local oscil-
lator.
Each of reference inputs may be selected to accept
either the auto-detect acceptable reference frequency
or manually acceptable reference frequency. Each
reference input is continuously monitored for activity
and frequency offset. The activity monitoring is
implemented with a leaky bucket accumulator. A
reference is designated as “qualified” if it is active and
its frequency offset FisuwnitchtiniotnhealpSropgeracmifmiceadtiroannge
for a pre-programmed time.
Active references may be selected manually or
automatically, individually selectable for T0 and T4. In
manual mode, the active reference is selected under
application control, independent of it’s qualification
status.
In automatic mode, the active reference is selected
according to revertivity status, and each reference’s
priority and qualification. Reference priorities are
individually programmable. T0 and T4 each have
their own priority tables. Revertivity determines
whether a higher priority qualified reference should
preempt a qualified current active reference.
All reference switches are performed in a hitless
manner. When references are switched, the device
will minimize phase transitions in the output clocks. A
frequency ramp control feature also ensures smooth
frequency transitions into/out of both freerun and
holdover mode.
STC5230 provides two modes to program the
frequency of CLK0~CLK8 (except CLK3 and CLK4)
individually: Freq Pre Defined mode (default mode)
and Freq User Defined mode. Phase skew of
CLK0~CLK8 and T0_XSYNC_OUT is programmable.
Timing generator T0 supports master/slave operation
for redundant applications. T0 sends both the
phase and reference selection information to the
other T0 of the paired STC5230s via the proprietary
SyncLink^TM cross-coupled data link. The STC5230
may determine and report the T0 round-trip phase
delay of the cross-couple data links.
The phase of the slave’s clock outputs may be
adjusted in 0.1ns step to compensate for the propa-
gation and re-transmission delay of the cross-couple
path. This will then minimize the phase hits to the
downstream devices resulting from master/slave
switches.
A serial bus interface (SPI) provides application
access to the STC5230’s internal control and status
registers.
Page 15 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011