STC5230_15 Datasheet, PDF (18/64 Pages) Connor-Winfield Corporation – Line Card Clock

STC5230
Synchronous Clock for SETS
Data Sheet
change and reference switches. An application pro-
grammable maximum slew rate of 1, 1.5, and 2 ppm/
second (or no slew rate limit) may be enforced, as
written to the T(0/4) History Ramp registers.
Freerun/Master Mode
The CLK(0-6,8) (CLK7 for T4) clock outputs are syn-
thesized and may be calibrated from MCLK and have
the stability of the external TCXO/OCXO. The calibra-
tion offset may be programmed by the application by
writing to the Freerun Cal register. The calibration
offset may be programmed from -102.4 to +102.3
ppm, in 0.1ppm steps.
Holdover/Master Mode
Holdover Mode is analogous to the freerun mode.
The CLK(0-6,8) (CLK7 for T4) clock outputs are syn-
thesized from MCLK with a frequency offset, which is
centered on the digitally calibrated freerun clock. The
clock outputs will have the stability of the external
TCXO/OCXO. The application may select the source
of the frequency offset from either a device accumu-
lated holdover history or a user supplied frequency
offset by writing the “HO_Usage” bit of the T(0/4)
Control Mode register. If the bit is set to Device
Accumulated History Holdover Mode, the DPLL
will use the device accumulated device holdover his-
tory to synthesize the clock outputs. If the bit is set to
User Supplied History Mode, the DPLL outputs are
synthesized according to an application supplied fre-
quency offset, as provided in the T(0/4) User Accu
History registers. To facilitate the user’s accumula-
tion of a holdover history, the user may read the
short-term history of the current clock outputs from
the T(0/4) Short Term Accu History register.
Synchronized/Master Mode
T0 timing generator is put into the Master mode by
bringing the T0_M/S pin high. T4 timing generator
only works in Master mode. In synchronized mode,
the DPLL phase-locks and tracks to the selected
input reference. The timing generator is in external-
timing mode. The CLK(0-6,8) (CLK7 for T4) clock
outputs are all synchronized to the selected input ref-
erence.
In this mode, the “Phase Align Mode” bit of the T(0/
4) Control Mode registers determines the output
clock to input reference phase alignment mode. If
both the bit is set to “Align” and frequency of the
active reference is 8kHz, this timing generator runs in
align mode, otherwise, it run in arbitrary mode. Run-
ning in arbitrary mode, the DPLL will initially operate
in frequency lockingFmuondcetiionnpaull-Sinppercoicfeicssa.tiWohnen
the frequency of the reference is determined and
locked, the clock output phase relationship relative to
the reference input will be rebuild and locked. If run-
ning in align mode, the output clocks are phase
aligned to the selected reference. (It should be noted
that output-to-reference phase alignment is meaning-
ful only in those cases where the output frequency
and reference are the same or related by an integer
ratio.)
After a reference switch or re-lock (due to loss of sig-
nal or loss of lock), the DPLL will be in a pull-in pro-
cess initially. If the phase mode is set to be “arbitrary”,
the pull-in process will be frequency-locking only until
the frequencies of the reference and output meet.
Then, the clock output phase relationship relative to
the reference input will be rebuild and locked. If the
phase mode is set to be aligned, the pull-in process
will be in phase-locking mode since the beginning.
The pull-in process may prologue to 60+ seconds in
normal situation.
Each DPLL’s loop bandwidth may be set indepen-
dently. Loop bandwidth is programmable from
100mHz to 103Hz by writing to the T(0/4) Bandwidth
registers.
There are two special cases of the synchronized
mode: (a) Zombie mode - If the signal of the active
reference is lost, the DPLL output is generated
according to the short-term history; and (b) Out of
Pull-in Range mode - If the selected reference
exceeds the pull-in range as programmed by the
application, the DPLL output may be programmed to
stay at the pull-in range limit, or to follow the refer-
ence. This is programmed by writing the “OOP” bit of
the T(0/4) Control Mode registers, specifying
whether to follow or not follow a reference that has
exceeded the pull-in range. The frequency offset is
relative to the digitally calibrated freerun clock.
Slave Mode
The slave mode is analogous to the synchronized/
master mode. T0 timing generator will enter this
mode by bringing the T0_M/S pin low. T4 timing gen-
erator does not support slave mode. Different from
the synchronized/master mode, the phase of the out-
put clock is aligned to the input cross-couple refer-
ence, not arbitrary. The loop bandwidth is fixed to 103
Hz. The DPLL’s clock outputs will follow the cross-ref-
Page 18 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011