STC5230_15 Datasheet, PDF (49/64 Pages) Connor-Winfield Corporation – Line Card Clock

Default value: 0
Field Value
7
8
9
CLK_User_Defined_Freq, 0x67 (R/W)
STC5230
Synchronous Clock for SETS
Data Sheet
Clock output
CLK7
CLK8
CLK3, CLK4,
T0_XSYNC_OUT
Address
Bit7
0x67
0x68
0x69
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits 0-7 of 18 bits Clock Frequency Selection in Freq User Defined mode
Bits 15-8 of 18 bits Clock Frequency Selection in Freq User Defined mode
Not used
Bits 17-16 of 18 bits Clock Frequency
Selection in Freq User Defined mode
Set to 0 and select associated clock index at the register CLK_Index_Selector to enable Freq Pre Defined
mode for CLK0~CLK8 individually.
Set to valid non-zero value to enable Freq User Defined mode and program frequency value from 1MHz to
156.25MHz, in 1kHz steps, for CLK0~CLK8 (except CLK3 and CLK4) based on which clock index is selected
at register CLK_Index_Select. CLK3 and CLK4 has the fixed frequency at 8kHz and 2kHz. Frequency of
T0_XSYNC_OUT is fixed as well.
Field Value
0
1~999
1000 ~ 156250
156251~262143
Default value: 0
CLK_Skew_Adj, 0x6a (R/W)
CLK frequency
Enable Freq Pre Defined mode
Do Not Use
1MHz ~ 156.25MHz
Do Not Use
Address
Bit7
0x6a
0x6b
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Lower 8 bits of Clock Phase Skew Adjustment
Not used
Higher 4 bits of Clock Phase Skew Adjustment
Adjust phase skew for CLK0~CLK8 and T0_XSYNC_OUT based on which clock index is selected at the regis-
ter CLK_Index_Select. Phase skew of CLK3, CLK4, and T0_XSYNC_OUT are adjusted simultaneously at
this register when T0_XSYNC_OUT is selected at the register CLK_Index_Select. The adjustment is from -
6400/128 ns to 6396.875/128 ns, which is -50ns ~ 49.976 ns, in 3.125/128 ns steps, 2’s complement.
Default value: 0
Page 49 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011