STC5230_15 Datasheet, PDF (59/64 Pages) Connor-Winfield Corporation – Line Card Clock

STC5230
Synchronous Clock for SETS
Data Sheet
Application Notes
This section describes typical application use of the STC5230 device. The General section applies to all appli-
cation variations.
General
Power and Ground
Well-planned noise-minimizing power and ground are essential to achieving the best performance of the
device. The device requires 3.3 digital power input. All digital I/O is at 3.3V, LVTTL compatible, except for the
two pairs of LVPECL clock outputs.
It is desirable to provide individual 0.1uF bypass capacitors, located close to the chip, for each of the power
input leads, subject to board space and layout constraints. On power-up, it is desirable to have the 3.3V either
lead or be coincident with.
Digital ground should be provided by as continuous a ground plane as possible.
Note: Un-used reference inputs must be grounded.
3.3V digital
power
inputs
STC5230
MCLK
Vdd33 (10)
OCXO/
TCXO
Vss (16)
Digital ground
(x) Number of pins
Figure 13: Power and Ground
An external 3.3V LVCMOS level clock (generally derived from TCXO or OCXO) is supplied at pin MCLK as
master clock. TCXO or OCXO should be carefully chosen as required by application. It is recommended that
the oscillator is placed close to the STC5230. Frequency of the master oscillator has four options, see descrip-
tion of the register MCLK Freq Reset for details.
Page 59 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011