STC5230_15 Datasheet, PDF (42/64 Pages) Connor-Winfield Corporation – Line Card Clock

T4_History_Ramp, 0x4d (R/W)
STC5230
Synchronous Clock for SETS
Data Sheet
Address
0x4d
Bit7
Not used
Bit6
Bit5
Bit4
Long Term History bandwidth
Holdover bandwidth and ramp controls for T4:
Bit3
Bit2
Short Term History bandwidth
Bit1
Bit0
Ramp control
0x4d, bits 6 ~ 4
0
1
2
3
4
5
6, 7
Long Term
History -3dB
Bandwidth
4.9 mHz
2.5 mHz
1.2 mHz
0.62 mHz
0.31 mHz
0.15 mHz
Reserved
0x4d, bits 3 ~ 2
0
1
2
3
0x4d, bits 1 ~ 0
0
1
2
3
Default value: 0x27 (1.2mHz; 0.64Hz; 2ppm/sec)
T4_Priority_Table, 0x4e (R/W)
Short Term
History -3dB
Bandwidth
1.3 Hz
0.64 Hz
0.32 Hz
0.16 Hz
Ramp control
No Control
1.0 ppm/sec
1.5 ppm/sec
2.0 ppm/sec
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x4e
Ref 2 Priority
Ref 1 Priority
0x4f
0x50
Ref 4 Priority
Ref 6 Priority
Ref 3 Priority
Ref 5 Priority
0x51
Ref 8 Priority
Ref 7 Priority
0x52
0x53
Ref 10 Priority
Ref 12 Priority
Ref 9 Priority
Ref 11 Priority
Reference priority for automatic reference selection mode. Lower values have higher priority:
0x4e - 0x53, 4 bits
0
Reference Priority
Disable reference
Page 42 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011