STC5230_15 Datasheet, PDF (30/64 Pages) Connor-Winfield Corporation – Line Card Clock

Register Descriptions and Operation
STC5230
Synchronous Clock for SETS
Data Sheet
General Register Operation
The STC5230 device has 1, 2, 3, and 4 byte registers. One-byte registers are read and written directly. Multiple
-byte registers must be read and written in a specific manner and order, as follows:
Multibyte register reads
A multibyte register read must commence with a read of the least significant byte first. This triggers a transfer
of the remaining byte(s) to a holding register, ensuring that the remaining data will not change with the continu-
ing operation of the device. The remaining byte(s) must be read consecutively with no intervening read/writes
from/to other registers.
Multibyte register writes
A multibyte register write must commence with a write to the least significant byte first. Subsequent writes to
the remaining byte(s) must be performed in ascending byte order, consecutively, with no intervening read/
writes from/to other registers, but with no timing restrictions. Multibyte register writes are temporarily stored in
a holding register, and are transferred to the target register when the most significant byte is written.
Clearing bits in the Interrupt Status Register
Interrupt event register Intr_Event bits are cleared by writing a “1” to the bit position to be cleared. Interrupt bit
positions to be left as is are written with a “0”.
Chip_ID, 0x00 (R)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x00
0x01
0x30
0x52
Indicates chip’s ID number
Chip_Rev, 0x02 (R)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x02
Revision Number
Indicates the revision number of STC5230. Refer to Order Information for current revision format.
Chip_Sub_Rev, 0x03 (R)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x03
Sub-Revision Number
Indicates the firmware revision number of STC5230. Refer to Order Information for current revision format.
Page 30 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011