STC5230_15 Datasheet, PDF (19/64 Pages) Connor-Winfield Corporation – Line Card Clock

STC5230
Synchronous Clock for SETS
Data Sheet
erence independent of the “OOP” bit of the T0 Con-
trol Mode registers. The DPLL will lock and phase
align on the T0_XSYNC_IN input.
Operating Mode Transition Details
When the reference selection is set to manual mode,
the operating mode is selected by writing to the T(0/4)
Manual Active Ref registers. This forces the timing
generator into freerun, synchronized, or holdover
mode.
When the reference selection is set to automatic
mode, the automatic reference selector picks the
active reference and decides the operating mode.
The DPLL will enter synchronized mode if at least
one reference is qualified and selected as the active
reference. Otherwise, the operating mode will be
either freerun mode or holdover mode, depending on
the availability of the holdover history.
Figure 2 shows the phase locked loop states and
transitions for operation with automatic reference
selection in Master mode. The transfer into and out of
holdover mode is designed to be smooth and free of
hits with frequency ramp control.
Freerun
No Reference
Available and
HO not Available
Any
Reference
Available
Locking
Frequency
Locked
Locked
Synchronized
No Reference Available
and HO Available
Switch to a
new active
reference
Any
Reference
Available
Holdover
Figure 2: Operating mode transition in automatic ref-
erence selection (Master mode)
On all transitions into freerun or back from freerun, an
application programmFaubnlecmtioaxnimalumSpsleecwifriacteatoifo1n,
1.5, or 2 ppm/second (or no slew rate limit) is applied,
as written to the T(0/4) History Ramp registers.
History Accumulation Details
Three holdover histories are built and maintained by
each timing generator: the short-term history, the
long-term history, and the device holdover history.
1. Short-Term History
This is a short-term average frequency of the DPLL’s
clock outputs. The weighted 3rd order low-pass filter
may be programmed for a -3dB point of 1.3 Hz, 0.64
Hz, 0.32 Hz, and 0.16 Hz by writing to the T(0/4) His-
tory Ramp register. The short-term history is used in
the zombie sub-mode. This history may be read from
the T(0/4) Short Term Accu History registers.
2. Long-Term History
This is a long-term average frequency of the DPLL’s
clock outputs, while synchronized to a selected exter-
nal reference. The weighted 3rd order low-pass filter
may be programmed for a -3dB point of 4.9 mHz, 2.5
mHz, 1.2 mHz, 0.62 mHz, 0.31 mHz, and 0.15 mHz
by writing to the T(0/4) History Ramp register. Inter-
nally, an express mode is used after reset by applying
a lower time constant for the first 15 minutes to speed
up the history accumulation process. This accumula-
tion process will be reset whenever the selected ref-
erence is switched or loss of lock occurs. The
accumulation process will then resume after synchro-
nization is achieved, as indicated by the assertion of
“SYNC” bit in the T(0/4) DPLL Status register. Addi-
tionally, the application may flush/rebuild this long-
term history by writing either “0” or “1” to the T(0/4)
Accu Flush register. The long-term history may be
read from the T(0/4) Long Term Accu History regis-
ters.
3. Device Holdover History
When the timing generator enters the holdover mode
with the history usage programmed as Device Accu-
mulated History Holdover Mode, this history deter-
mines the CLK(0-6,8) (CLK7 for T4) clock outputs.
The initial history will begin and be continuously
updated by the long-term history after the completion
of the 15 minute express mode time. Updating will
stop if the long term history accumulation process is
reset as a result of a reference switch or loss of lock.
Thus, the previous holdover history will persist until a
Page 19 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011