STC5230_15 Datasheet, PDF (51/64 Pages) Connor-Winfield Corporation – Line Card Clock

Bus_Loader_Status, 0x70 (R)
STC5230
Synchronous Clock for SETS
Data Sheet
Address
Bit7
0x70
Bit6
Bit5
Bit4
Reserved
Bit3
Bit2
Bit1
Bit0
load
complete
Bus ready
Checksum
status
If bus mode has been selected with pins LM0,1, this register indicates the loader’s status.
Load complete
Bus ready
Checksum status
Set to 1 when the loading process is complete in the bus mode.
Set to 1 when the device is ready to load data in the bus mode.
Set to 1 if the hardware and firmware configuration data load is successful (CRC-16
checksum over the 10,496 bytes of hardware and firmware configuration data
passes) in the bus mode. The “checksum status” bit is valid only after the “load com-
plete” bit has been set.
Bus_Loader_Data, 0x71 (W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x71
Data
If bus mode has been selected with pins LM0,1, the hardware and firmware configuration data is written to this
register.
Bus_Loader_Counter, 0x72 (R)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x72
Lower 8 bits of bus loader counter
0x73
Reserved
Higher 6 bits of bus loader counter
If bus load data mode has been selected with pins LM0,1, this register indicates the number of bytes that have
been written to the Bus_Loader_Data register.
Bus_Core_Status, 0x75 (R)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x75
Reserved
Checksum
status
If bus load data mode has been selected with pins LM0,1, this register indicates the checksum status of the
core configuration data loading process from the bus interface.
Checksum status
Set to 1 if the core configuration data loading is successful in the Bus interface
mode.
Page 51 of 64 TM103 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011