STC5230_15 Datasheet, PDF (31/64 Pages) Connor-Winfield Corporation – Line Card Clock

T0_MS_Sts, 0x04 (R)
STC5230
Synchronous Clock for SETS
Data Sheet
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x04
Not used
T0 M/S
Reflects the states of the pin T0_MS. 1 = Master, 0 = slave
T0_Slave_Phase_Adj, 0x05 (R/W)
Address
Bit7
0x05
0x06
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Adjust T0 slave phase from 0 ~ 409.5 ns in 0.1 ns steps, lower 8 bits
Not used
Adjust T0 slave phase from 0 ~ 409.5 ns in 0.1 ns steps,
upper 4 bits
The T0 slave phase may be adjusted 0 to 409.5 ns relative to the cross couple input with 0.1 ns resolution. This
is a 12 bit register, split across address 0x05 and 0x06.
Default value: 0
Fill_Obs_Window, 0x09 (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x09
Not used
Leaky bucket fill observation window, m = 0 ~ 15
Sets the fill observation window size for the reference activity monitor to (m+1) ms. The window size can be set
from 1ms to 16ms.
Default value: m = 0, (1ms)
Leak_Obs_Window, 0x0a (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x0a
Not used
Leaky bucket leak observation window, n = 0 ~ 15
Sets the leak observation window size for the reference activity monitor to (n + 1) times the fill observation win-
dow size.
Default value: n = 3, (4 times)
Bucket_Size, 0x0b (R/W)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x0b
Not used
Leaky bucket size, 0 ~ 63
Sets the leaky bucket size for the reference activity monitor. Bucket size equal to 0 will set the activity monitor
off, which will not have the leaky bucket alarm assert or de-assert threshold. Otherwise, the bucket size must
be greater than or equal to the alarm assert value. Invalid values will not be written to the register.
Page 31 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011