STC5230_15 Datasheet, PDF (62/64 Pages) Connor-Winfield Corporation – Line Card Clock

Revision
P1.1
2.0
2.1
STC5230
Synchronous Clock for SETS
Data Sheet
Change Description
Change 125MHz of CLK1 to 19.44MHz
Change 125MHz of CLK2 to 15.625MHz
Note 19.44MHz of CLK1 is low noise output
Correct bits range of CLK1_Sel and CLK2_Sel to 3-0
Add description of register 0x75 to register map
Remove the address of registers from detail description.
Change section title of Field Upgradability to Configuration Data Load and
Field Upgradability and rewrite the section
Correct R/W of the register T0_T4_MS_Sts to R (read only)
Add description for Revertive and Manual/Auto bit of register 0x1c and
0x39
Add a new section of Specification Modification to note the frequency
change for CLK1 and CLK2
Refine register map description
Correct SPI pins name in Processor Interface Descriptions
Correct bits 3-0 description of register Leak_Obs_Window
Refine register detail description of T(0/4)_PLL_Status
Change disable to tri-state for clock outputs
Update section of Specification Modification
Add ITU G.8262 EEC opt1 and opt 2
Pages
6, 10, 17, 37
6, 10, 17, 37
6
10, 37
10
12, 13, 14,
15, 16, 18,
19
19, 20, 21
24
28, 32
46
9, 10
22
25
32, 37
37, 38, 39,
40
47
1
Page 62 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011