STC5230_15 Datasheet, PDF (37/64 Pages) Connor-Winfield Corporation – Line Card Clock

T0_User_Accu_History, 0x2c (R/W)
STC5230
Synchronous Clock for SETS
Data Sheet
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x2c
Bits 0 - 7 of 32 bit User Holdover History
0x2d
Bits 8 - 15 of 32 bit User Holdover History
0x2e
Bits 16 - 23 of 32 bit User Holdover History
0x2f
Bits 24 - 31 of 32 bit User Holdover History
User accumulated history for T0 relative to MCLK. 2’s complement. Resolution is 0.745x10^-3 ppb.
Default value: 0
T0_History_Ramp, 0x30 (R/W)
Address
0x30
Bit7
Not used
Bit6
Bit5
Bit4
Long Term History Bandwidth
Holdover bandwidth and ramp controls for T0:
Bit3
Bit2
Short Term History Band-
width
Bit1
Bit0
Ramp control
0x30, bits 6 ~ 4
0
1
2
3
4
5
6, 7
Long Term
History -3dB
Bandwidth
4.9 mHz
2.5 mHz
1.2 mHz
0.62 mHz
0.31 mHz
0.15 mHz
Reserved
0x30, bits 3 ~ 2
0
1
2
3
Short Term
History -3dB
Bandwidth
1.3 Hz
0.64 Hz
0.32 Hz
0.16 Hz
0x30, bits 1 ~ 0
0
1
2
3
Default value: 0x27 (1.2mHz; 0.64Hz; 2ppm/sec)
Ramp control
No Control
1.0 ppm/sec
1.5 ppm/sec
2.0 ppm/sec
Page 37 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011