STC5230_15 Datasheet, PDF (63/64 Pages) Connor-Winfield Corporation – Line Card Clock

Revision
3.0
STC5230
Synchronous Clock for SETS
Data Sheet
Change Description
Add RoHS 6/6 compliant
Add description of supporting four programmable frequencies of external
oscillator
Add description of supporting manually acceptable frequency on
Ref1~Ref12
Change pin AVdd18, Vdd18, T4_XSYNC_IN, T4_MS, T4_XSYNC_OUT,
AVss, AVdd18, and PNC to NC
Change NC pin description
Remove 1.8V digital and analog power input
Replace 62.5MHz with 125MHz on CLK1 and CLK2
Remove low noise 19.44MHz on CLK1 and 15.625MHz on CLK2
Change register name of Ref_Selector to Ref_Index_Selector;
Ref_Frq_Offset to Ref_Info;
Remove register T4_Slave_Phase_Adj
Remove bit13 of register Refs_Activity
Remove bit7,6 of register Intr_Enable and Intr_Event
Remove Bit3 of the register CLK1_Sel and CLK2_Sel
Add register CLK_Index_Select, CLK_User_Defined_Freq,
CLK_Skew_Adj, Manual_Accept_Ref_Freq, MCLK_Freq_Reset
Add description of Freq Pre Defined mode and Freq User Defined mode
Modify detail diagram of output clocks Figure 5
Change disable to tristate for CLK0~CLK8
Modify Order Information
Rewrite section of specification modification
Change mechanical specifications due to assembly change
Pages
1, 58
1, 13, 15, 17
1, 14, 15, 20,
21
5, 6, 7
7
1, 8, 59
6, 10, 19, 22,
43, 44
6, 10, 19, 22,
43, 44
9, 13, 19, 32,
9, 30
9, 33
10, 46
10, 45, 46
11, 49, 50, 51
15, 22, 23
22
11, 23, 24,
45, 46, 47,
48
57
58
60
Page 63 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011