STC5230_15 Datasheet, PDF (25/64 Pages) Connor-Winfield Corporation – Line Card Clock

STC5230
Synchronous Clock for SETS
Data Sheet
Activity of the signals on the T0_XSYNC_IN pin is
available in the Refs Activity register. (The leaky
bucket algorithms are not applied to these signals.)
Once a pair of timing generators has been operating
in aligned master/slave mode, and a master/slave
switch occurs, the timing generator that becomes
master will maintain its output clock phase and fre-
quency while a phase rebuild is performed on its
selected reference input. Therefore, as master mode
operation commences, there will be no phase or fre-
quency hits on the clock outputs. Assuming the phase
offset is programmed for the actual delay of this
cross-couple path, there will again be no phase hits
on the output clocks of the timing generator that has
transitioned from master to slave.
Event Interrupts
The STC5230 may indicate the occurrence of a num-
ber of events as an interrupt to the host processor via
pin EVENT_INTR (pin 32). The user may enable or
disable individual interrupt by writing to register Intr
Enable. The associated events which trigged inter-
rupts will be latched. After detected the assert of inter-
rupt pin, the application may read the list of latched
events from register Intr Event. The user may clear
the events by writing a ‘1’ to the bit position of each
related event. The pin EVENT_INTR returns to nor-
mal when all events are cleared.
registers and DPLL detailed behavior. The hardware
and firmware configuFruatniocntidoantaaml Saypbeecilofiacdaetdiofrnom
the internal ROM (programmed by factory), an
optional external EEPROM, or from the bus interface.
If the load failed, the application must rest the device
and repeat the load process. Loading external hard-
ware and firmware configuration data via optional
external EEPROM or the bus interface may provide
the feature of field Upgradability to applications.
Hardware and firmware configuration data loading
method depends on the configuration pins.
Configuration Pins
The configuration pins LM0 and LM1 determine the
hardware and firmware configuration data loading
method following a power-up or reset. LM0 and LM1
also allow the application to switch among the con-
troller of ROM, EERPOM and Bus interface in run
time. The combination of configuration pins is shown
in Table 5.
Note that the configuration pins should not both be
high, as device damage may occur.
Table 7: Configuration Pins
LM1
0
LM0
0
Description
ROM mode
There are 10 different events that can trigger an inter-
rupt. These include any status change of either timing
generator and the change of qualification status of
input references. The status change of a timing gen-
erator includes a change of the active reference in
automatic reference selection mode, a change of the
DPLL status, and a change of the cross reference
activity. Each event may be enabled and disabled
individually.
Configuration Data Load and Field
Upgradability
Following any device reset, either via power-up or
operation of the reset pin, the device needs to be
loaded with the configuration data. The loading proce-
dure has two stages. First stage is to load core con-
figuration data (programmed with factory default).
The register ROM Core Status may provide the sta-
tus of the core configuration data loading process.
Second stage is to load hardware and firmware con-
figuration data. This data defines the initialization of
0
1
1
0
1
1
Bus mode
EEPROM mode
Reserved - do not use
ROM Mode
When the ROM mode is configured via LM0 and LM1
following a power-up or reset, the hardware and firm-
ware configuration data may be loaded automatically
from the internal ROM. The data is programmed by
manufacturer. Hardware and firmware configuration
data loading via the ROM mode is accomplished
using register ROM Loader Status. The register pro-
vides the status of the core, hardware and firmware
configuration data loading process.
Bus Mode
When the Bus Mode is configured via LM0 and LM1
following a power-up or reset, the hardware and firm-
ware configuration data may be loaded from the SPI
bus interface using the registers Bus Loader Status,
Page 25 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011