STC5230_15 Datasheet, PDF (6/64 Pages) Connor-Winfield Corporation – Line Card Clock

STC5230
Synchronous Clock for SETS
Data Sheet
STC5230 Pin Description
All I/O is LVCMOS, except for CLK0 and CLK8, which are LVPECL.
Pin Name
Vdd33
Vss
TRST
TCK
TMS
TDI
TDO
RESET
MCLK
SPI_CS
SPI_SCK
SPI_SDI
SPI_SDO
EEP_SO
EEP_SI
EEP_SCK
EEP_CS
EVENT_INTR
REF1
REF2
REF3
REF4
REF5
REF6
REF7
REF8
REF9
REF10
Table 1: Pin Description
Pin #
I/O
Description
6,22,31,
44,59,61,
69,80,
87,97
3.3V power input
3,13,15,
20,29,35,
41,56,64,
67,71,78,
82,88,95
Digital ground
94
I JTAG boundary scan reset, active low
93
I JTAG boundary scan clock
91
I JTAG boundary scan mode selection
90
I JTAG boundary scan data input
89
O JTAG boundary scan data output
30
I Active low to reset the chip
99
I Master clock input, 20 MHz
45
I SPI bus chip select (CS)
46
I SPI bus clock input (SCLK)
50
I SPI bus data input (SDI)
51
O SPI bus data output (SDO)
37
I/O Optional external EEPROM SO
36
I/O Optional external EEPROM SI
34
I/O Optional external EEPROM SCK
33
I/O Optional external EEPROM CS
32
O Event interrupt
2
I Reference input 1
4
I Reference input 2
5
I Reference input 3
8
I Reference input 4
10
I Reference input 5
12
I Reference input 6
14
I Reference input 7
16
I Reference input 8
17
I Reference input 9
19
I Reference input 10
Page 6 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011