STC5230_15 Datasheet, PDF (20/64 Pages) Connor-Winfield Corporation – Line Card Clock

STC5230
Synchronous Clock for SETS
Data Sheet
new long term history is accumulated following a ref-
erence switch or the attendant re-building of the long
term history after loss of lock. The “AHR” bit of the
T(0/4) DPLL Status registers is set to “1” during
updating, but will revert to “0” when updating stops.
Additionally, the application may reset this holdover
history by writing “1” to the T(0/4) Accu Flush regis-
ter.
Phase-Locked Loop Status Details
The T(0/4) PLL Status registers contain the detailed
status of the DPLLs, including the signal activity of the
active reference, the synchronization status, and the
availability of the holdover histories.
Applications can program the Intr Enable register to
enable/disable the interrupts (pin EVENT_INTR)
trigged by the status change of the T(0/4) PLL Status
registers.
SYNC bit
In external-timing mode (e.g., slave and synchro-
nized/master modes), this bit indicates the achieve-
ment of synchronization. This bit will not be asserted
in self-timing mode (e.g., freerun and holdover
modes).
LOS bit
In external-timing mode (e.g., slave and synchro-
nized/master modes), this bit indicates the loss of sig-
nal on the active reference. This bit will not be
asserted in self-timing mode (e.g., freerun and hold-
over modes).
LOL bit
In external-timing mode (e.g., slave and synchro-
nized/master modes), the DPLL will set this bit if it
fails to achieve or maintain lock to the active refer-
ence. This bit will not be asserted in self-timing mode
(e.g., freerun and holdover modes). This bit is also
not complementary to the SYNC bit. Both bits will not
be asserted when the DPLL is in the pull-in process.
OOP bit
This bit indicates that the active reference is out of the
pull-in range. This is meaningful only if in external-
timing mode (e.g., slave and synchronized/master
modes). This bit will not be asserted in self-timing
mode (e.g., freerun and holdover modes). The fre-
quency offset is relative to the digitally calibrated fre-
erun clock.
SAP bit
Functional Specification
This bit when set indicates that the DPLL’s output
clocks have stopped following the active reference
because the frequency offset of the active reference
is out of pull-in range. The application can write to the
T(0/4) Control Mode register to program whether the
DPLL shall follow the active reference outside of the
specified pull-in range.
AHR bit
This bit indicates whether the device holdover history
is tracking on the current active reference (updating
by the long-term history).
HHA bit
This bit indicates the availability of the holdover his-
tory, which may be either the user provided history or
the device holdover history.
Reference Inputs Details
The STC5230 accepts 12 external reference inputs.
The reference inputs may be selected to accept either
the auto-detect acceptable reference frequency which
can be automatically detected by STC5230 or manu-
ally acceptable reference frequency. All 12 reference
inputs are monitored continuously for frequency,
activity and quality. Each timing generator may select
any of the reference inputs when the device is in
external timing mode. T4 may accept T0’s output as
its input via internal feedback path.
Acceptable Frequency and Frequency Offset
Detection
The STC5230 can automatically detect the frequency
of the reference input when the user enable the auto-
detection function for Ref1~Ref12 individually at the
register Ref Index Selector and Manual Accept Ref
Freq. The acceptable auto-detect frequencies are:
8kHz, 64kHz, 1.544MHz, 2.048MHz, 19.44MHz,
38.88MHz, 77.76MHz, 6.48MHz, 8.192MHz,
16.384MHz, 25MHz, 50MHz or 125MHz. These fre-
quencies can be automatic detected continuously in
the detector. Any carrier frequency change will be
detected within 1ms. Each input is also monitored for
frequency offset between input and the internal fre-
erun clock. The frequency offset is a key factor to
determine qualification of the reference inputs. See
register Ref Index Selector and Ref Info.
STC5230 provides another option which allows the
Page 20 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011