STC5230_15 Datasheet, PDF (17/64 Pages) Connor-Winfield Corporation – Line Card Clock

STC5230
Synchronous Clock for SETS
Data Sheet
Detailed Description
Chip Master Clock
The device operates with an external oscillator (e.g.,
OCXO or TCXO) as its master clock, connected to
the MCLK input, pin 99. Generally, user should select
an oscillator has great stability and low phase noise
as the master clock (MCLK).
The STC5230 supports four different accepted fre-
quencies of master clock: 10MHz, 12.8MHz,
19.2MHz, and 20MHz. Initial default accepted fre-
quency of MCLK for STC5230 is 20MHz. When
10MHz, 19.2MHz, or 20MHz is selected as the fre-
quency of MCLK, the user must write register MCLK
Freq Reset three times consecutively, with no inter-
vening read/writes from/to other register. An internal
soft-reset will occur after three writes completed. The
accepted frequency of MCLK input returns to 20MHz
following any regular reset. See register MCLK Freq
Reset for details.
This feature allow the user can digitally calibrate the
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Operating Mode General Description
The STC5230 includes both a T0 and T4 timing gen-
erators. Each timing generator has its own DPLL.
In general, each timing generator may individually be
either in external-timing or self-timing mode. In exter-
nal-timing mode, a timing generator may select any of
the external references as the active reference for the
DPLL. The active reference can be either one of the
12 input reference clocks, or the reference from the
T0_XSYNC_IN cross-coupled links in slave mode,
when devices are operated as master/slave pairs. In
addition, T4 may select the output of T0 as its active
reference. In self-timing mode, the clock outputs are
synthesized from the MCLK (the external TCXO/
OCXO) (with a programmable calibration) or a given
frequency offset.
In the meantime, the STC5230 allows user to read
three values at the register MCLK Freq Reset:
FRQID, COUNT, and ID Written Value.
FRQID
Indicates the ID of the frequency of MCLK that the
STC5230 currently accept.
COUNT
Indicates how many times the register MCLK Freq
Reset has been written to.
ID Written Value
Indicates the ID of associated value that is being writ-
ten to the register MCLK Freq Reset.
See the register MCLK Freq Reset for more details.
Freerun Clock
The STC5230 has an internal freerun clock synthe-
sized from the MCLK. The frequency offset of the
internal freerun clock can be calibrated by writing to
the register Freerun Cali. It has the stability of the
external TCXO/OCXO. The calibration offset may be
programmed in 0.1ppm steps from -102.4 to
+102.3ppm, in 2’s complement.
In master mode, the timing generators may each
operate in Freerun, Synchronized, or Holdover
mode. Operating T0 timing generator in the slave
mode is analogous to the synchronized/master. Both
are in external-timing mode. In synchronized/master
mode, the phase relationship between the reference
and the clock outputs may be configured as arbitrary
or aligned. The user may also program the DPLL’s
loop bandwidth to vary the noise transfer function. In
slave mode, the clock outputs phase-align to the
cross-reference, and the loop bandwidth is fixed (103
Hz).
Holdover mode is analogous to the freerun mode.
Both are self-timing modes. The clock outputs are
synthesized from the local oscillator with a program-
mable calibration or a given frequency offset. The sta-
bility in these two modes is simply determined by the
local oscillator.
Operating Mode Details
The STC5230 is designed to provide phase and fre-
quency hit-less clock outputs to downstream devices,
even through operating mode change and reference
switches. Both the phase and frequency transitions
will be continuous. The transfer into the self-timing
mode (freerun and holdover) is designed to be fre-
quency bump-less. A frequency ramp control limits
the rate of frequency change through operating mode
Page 17 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011