STC5230_15 Datasheet, PDF (46/64 Pages) Connor-Winfield Corporation – Line Card Clock

STC5230
Synchronous Clock for SETS
Data Sheet
Default value: 63
CLK5_Sel, 0x5b (R/W)
0x5a, bits 5 ~ 0
0
1 ~ 62
63
CLK4 (2kHz) output
Tri-state
Pulse width 1 to 62 cycles of 155.52MHz
50% duty cycle
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x5b
Not used
CLK5 Select
Selects frequency of CLK2 or put CLK2 in tri-state in Freq Pre Defined mode. Freq Pre Defined mode (default
mode) of CLK5 is enabled by setting the register CLK_Index_Select to CLK5 and the register
CLK_User_Defined_Freq to 0.
Default value: 2 (44.736MHz)
CLK6_Sel, 0x5c (R/W)
0x5b, bits 1 ~ 0
0
1
2
3
CLK5 output
Tri-state
44.736MHz (DS3)
34.368MHz (E3)
Reserved
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x5c
Not used
CLK6 Select
Selects frequency of CLK6 or put CLK6 in tri-state in Freq Pre Defined mode. Freq Pre Defined mode (default
mode) of CLK6 is enabled by setting the register CLK_Index_Select to CLK6 and the register
CLK_User_Defined_Freq to 0.
0x5c, bits 3 ~ 0
0
1
2
3
4
5
6, 7, 8
9
10
11
12
13
14, 15
CLK6 output
Tri-state
2.048MHz
4.096MHz
8.192MHz
16.384MHz
32.768MHz
Reserved
1.544MHz
3.088MHz
6.176MHz
12.352MHz
24.704MHz
Reserved
Page 46 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011