STC5230_15 Datasheet, PDF (50/64 Pages) Connor-Winfield Corporation – Line Card Clock

Manual_Accept_Ref_Freq, 0x6c (R/W)
STC5230
Synchronous Clock for SETS
Data Sheet
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0x6c
0x6d
Not used
Lower 8 bits of integer N Select
Higher 7 bits of integer N Select
Enable frequency auto detect function or set integer N for the manual acceptable reference frequency for
Ref1~Ref12 individually.
Setting this register to 0 to enable the automatic detection for reference input frequency. The auto-detect
acceptable reference input frequencies are shown in Table 3.
Select the integer N for the manually acceptable reference at frequency of Nx8kHz (N is integer from 1 to
32767) for REF1 ~ REF12. Which of reference input is selected for the manually acceptable reference is
depending on the index selected at the register Ref_Index_Selector.
Setting integer N (from 1 to 32767) at this register allows user to manually select the acceptable reference
input frequency at the integer multiple of 8kHz, range from 8kHz to 262.136MHz. For instance, user can select
integer N = 32000 to manually accept frequency at 32000x8kHz = 256MHz.
Default value: 0
ROM_Core_Status, 0x75 (R)
Field Value
0
1~32767
Integer N Select
Enable auto detection for reference
input
Integer N for the manual acceptable
reference frequency
Address
Bit7
0x75
Bit6
Bit5
Bit4
Reserved
Bit3
Bit2
Bit1
Bit0
Hardware and Firmware
Configuration Checksum
Core Configuration
Checksum
If ROM mode has been selected with pins LM0,1, this register indicates the status of core, hardware and firm-
ware configuration data loading via internal ROM.
Core configuration checksum
Set to 1 when the core configuration data loading process is complete and
passed.
Hardware and configuration checksum
Bit2
Bit1
Status
0
0
Fail
0
1
Fail
1
0
Fail
1
1
Pass
Page 50 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011