STC5230_15 Datasheet, PDF (23/64 Pages) Connor-Winfield Corporation – Line Card Clock

STC5230
Synchronous Clock for SETS
Data Sheet
Freq Pre Defined Mode
This mode is enabled for CLK0~CLK8 (except CLK3
and CLK4) individually when associated clock output
index is selected at the register CLK Index Select
and the register CLK User Defined Freq is set to 0.
In Freq Pre Defined mode, clock outputs of CLK0 ~
CLK8 (except CLK3 and CLK4) are programmable for
some certain frequencies at the registers CLK(0~8)
Sel. This mode is only enabled when value of the reg-
ister CLK User Defined Freq is 0. Each clock of
CLK0 ~CLK8 can be put in tri-state by writing 0 to
registers CLK(0~8) Sel individually. Freq Pre Defined
mode is default manner for frequency selection of
clock outputs.
In this mode, supported pre-defined frequency of
CLK0~CLK8 is shown below:
• CLK0: 155.52/125 MHz (LVPECL), selected
or put it in tri-state by writing the CLK0 Sel
register.
• CLK1: programmable at 19.44MHz,
38.88MHz, 51.84MHz, 77.76 MHz, 25MHz,
50MHz, 125MHz, and tri-state, by writing to
the CLK1 Sel register.
• CLK2: Programmable at 19.44MHz,
38.88MHz, 51.84, 77.76 MHz, 25MHz,
50MHz, 125MHz and tri-state, by writing to
the CLK2 Sel register.
• CLK3: 8kHz, 50% duty cycle or programma-
ble pulse width, and may be put in tri-state by
writing to the CLK3 Sel register.
• CLK4: 2kHz, 50% duty cycle or programma-
ble pulse width, and may be put in tri-state by
writing to the CLK4 Sel register.
• CLK5: Either DS3 or E3 rate, or “tri-state”,
programmed by writing to the CLK5 Sel reg-
ister.
• CLK6: Programmable at nxT1 or nxE1 rate,
where n=1,2,4,8,16, or may be put in tri-state,
by writing to the CLK6 Sel register.
• CLK8: the second pair of 125 MHz
(LVPECL), put in tri-state by writing the CLK8
Sel register.
• CLK7 (T4): Either DS1 or E1 rate, or “tri-
state”, programmed by writing to the CLK7
Sel register.
Functional Specification
2kHz
8kHz
38.88MHz
77.76MHz
T1/E1
DS3/E3
Figure 6: T0 clock output Phase Alignment
In addition, the T0_XSYNC_OUT output provides
phase information and state data for master/slave
operation of the T0 timing generator.
CLK3, 5 and 6 are phase aligned with CLK4 (2kHz)
and 19.44MHz, 38.88MHz, 51.84MHz, 77.76MHz of
CLK1 and CLK2 are also phase aligned with CLK4
as shown in Figure 6. 25MHz, 50MHz, 125MHz on
CLK1 is not aligned with CLK4. 25MHz, 50MHz,
125MHz on CLK2 is not aligned with CLK4 too.
CLK0 and 8 are synchronized to CLK1~6, but not
phase aligned.
Freq User Defined Mode
Any valid non-zero value of the register CLK User
Defined Freq enable Freq User Defined mode and
output clock at associated frequency based on which
clock is selected at the register CLK Index Select. In
Freq User Defined Mode, the frequency of
CLK0~CLK8 (except CLK3 and CLK4) is programma-
ble from 1MHz to 156.25MHz, in 1kHz steps. It sup-
ports more flexible choices of frequencies than Freq
Pre Defined mode.
In Freq User Defined mode, any of clock outputs
(except CLK7 derived from synthesizer G₇ of T4
DPLL) which has frequency at the integer multiple of
8kHz is in phase alignment with the frame pulse out-
put CLK3 (8KHz) if none of clock phase skew is pro-
grammed.
Clock Skew Adjustment
The STC5230 allows user to program the phase skew
of each clock output, up and down 50ns in roughly
0.024ns steps. at the register CLK Skew Adj. Select
clock index at the register CLK Index Select to adjust
phase skew of associated clock output CLK0~CLK8
and T0_XSYNC_OUT.
Page 23 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011