STC5230_15 Datasheet, PDF (26/64 Pages) Connor-Winfield Corporation – Line Card Clock

STC5230
Synchronous Clock for SETS
Data Sheet
Bus Loader Data, Bus Loader Counter and Bus
Core Status. The hardware and firmware configura-
tion data is provided to the customer per an agree-
ment with the manufacturer. The application shall
follow the procedure below:
/* --- *
The data array data[10496] contains the hardware/firmware
configuration data, starting from index 0.
* --- */
Procedure Bus_Load
begin
Label_Repeat:
- busy wait until bit “bus ready” in the
Bus_Loader_Status is equal to ‘1’;
- for i: = 0 to 10,495 step 1
begin
- write data[i] to register Bus_Loader_Data;
- busy wait until bit “bus ready” in register
Bus_Loader_Status is equal to ‘1’;
end
- if bit “load complete” in register Bus_Loader_Status is
equal to ‘0’
begin
/* loading failed */
- reset this device by asserting pin RESET;
- goto Label_Repeat;
end
- if bit “checksum status” in register
Bus_Loader_Status is equal to ‘0’
begin
/* loading failed */
- reset this device by asserting pin RESET;
- goto Label_Repeat;
end
Before the “bus ready” bit is asserted or after the
“load complete” bit inFurengcisttieornBaulsSLpoeacdiefricSatatitousnis
asserted, all writes to the Bus Loader Data register
will be ignored.
At any time in the process, the application may read
the number of bytes that have been written from the
Bus Loader Counter register.
The register Bus Core Status provides the status of
core configuration data loading process.
EEPROM Mode
When EEPROM mode is configured via the LM0,
LM1 pins, the device may be ready for two pro-
cesses: hardware and firmware configuration data
load process, EEPROM upload and read back pro-
cess. For the hardware and firmware configuration
data load process, the data may be loaded from the
optional external EEPROM by the device’s built-in
EEPROM loader automatically following a power-up
or reset. The hardware and firmware configuration
data is provided to the customer per an agreement
with the manufacturer. Read and check the register
EEP Loader Checksum which indicates the CRC-16
checksum status of the loading process. The register
EEP Core Status indicates the checksum status of
the core configuration data loading process.
For upload and read back process, the application
may read and write the hardware and firmware con-
figuration data from/to the external EEPROM via
device’s EEPROM controller using the register EEP
Controller Mode, EEP Controller Cmd, EEP Con-
troller Page, and EEP Controller Data.
/* Bus Loading Success */
end of procedure Bus Load
The device will assert the “load complete” bit in regis-
ter Bus Loader Status after the application writes
10,496 bytes into register Bus Loader Data.
After the bit “load complete” is asserted, the applica-
tion shall read and check the bit “checksum status” of
register Bus Load Status. “1” indicates the check-
sum passed; “0” indicates a load failure. CRC-16
checksum encryption is used in the hardware/firm-
ware configuration data to assure the detection of
transmission error.
After uploading the complete hardware and firmware
configuration data to the external EEPROM, the appli-
cation should read it back and perform the compari-
son to ensure no transmission errors have happened.
The uploading and read back procedures are as fol-
low:
Procedure EEP_Upload
begin
/* --- *
The data array data[10496] contains the hardware/
firmware configuration data, starting from index 0.
* --- */
- busy wait until bit “ready” in register
EEP_Controller_Mode is equal to ‘1’;
- write 0x01 to register EEP_Controller_Mode;
/* turn on the write feature */
- write 0x00 to register EEP_Controller_Cmd;
Page 26 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011