STC5230_15 Datasheet, PDF (11/64 Pages) Connor-Winfield Corporation – Line Card Clock

Addr
0x4d
Reg Name
T4_History_Ramp
0x4e
0x54
0x55
0x56
0x57
T4_Priority_Table
T4_PLL_Status
T4_Accu_Flush
CLK0_Sel
CLK1_Sel
0x58 CLK2_Sel
0x59
0x5a
0x5b
0x5c
0x5d
0x5e
0x60
0x62
0x65
0x66
CLK3_Sel
CLK4_Sel
CLK5_Sel
CLK6_Sel
CLK7_Sel
Intr_Event
Intr_Enable
T0_MS_PHE
CLK8_Sel
CLK_Index_Select
0x67
0x68
0x69
0x6a
0x6b
0x6c
0x6d
0x7F
CLK_User_Defined_Freq
CLK_Skew_Adj
Manual_Accept_Ref_Freq
MCLK_Freq_Reset
STC5230
Synchronous Clock for SETS
Data Sheet
Table 4: Register Map
Bits
6-0
47-0
7-0
0-0
1-0
2-0
2-0
5-0
5-0
1-0
3-0
1-0
8-9,5-0
8-9,5-0
19-0
1-0
2-0
17-0
Type
R/W
R/W
R
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
Description
Controls T4 long term history and short term history accumulation
bandwidth and the locking stage’s frequency ramp control
REF1-12 selection priority for automatic mode (T4)
T4 PLL status SYNC, LOS, LOL, OOP, SAP, AHR, HHA
Flush/reset the long-term and the device holdover history for T4
155.52/125 MHz or tri-state for CLK0 (Freq Pre Defined mode)
19.44/38.88/51.84/77.76/25/50/125MHz or tri-state select for CLK1
(Freq Pre Defined mode)
19.44/38.88/51.84/77.76/25/50/125 MHz or tri-state select for CLK2
(Freq Pre Defined mode)
8kHz output 50% duty cycle or pulse width selection for CLK3
2kHz output 50% duty cycle or pulse width selection for CLK4
DS3/E3 select for CLK5 (Freq Pre Defined mode)
DS1 x n / E1 x n select for CLK6 (Freq Pre Defined mode)
DS1/E1 select for CLK7 (Freq Pre Defined mode)
Interrupt event
Interrupt enable
Round-trip phase delay of T0’s cross-couple data links
125 MHz clock enable or disable for CLK8 (Freq Pre Defined mode)
Determine which clock output is selected to program frequency in
Freq User Defined mode or adjust phase skew for clock output.
Enable Freq Pre Defined mode or select clock output frequency in
Freq User Defined mode for CLK0~CLK8 (except CLK3 and CLK4)
11-0
14-0
7-0
R/W Adjust phase skew for CLK0~CLK8 and T0_XSYNC_OUT
R/W Select integer N for manually acceptable frequency at Nx8kHz;
Enable auto detection of reference input frequency
R
Select the frequency of the external oscillator
Extra Registers if Configuration Data Mode is set as ROM_MODE
0x75 ROM_Loader_Status
2-0
R
Checksum status of core, hardware and firmware configuration data
Extra Registers if Configuration Data Mode is set as BUS_MODE
0x70 Bus_Loader_Status
2-0
R
Loading status of the hardware and firmware configuration data
0x71 Bus_Loader_Data
7-0
W Data port of the bus loader of the hardware and firmware configura-
tion data
0x72 Bus_Loader_Counter
13-0
R
Data counter of the bus loader of the hardware and firmware config-
uration data
0x75 Bus_Core_Status
0-0
R
Checksum status of core configuration data
Extra Registers if Configuration Data Mode is set as EEP_MODE
0x70 EEP_Loader_Checksum
0-0
R
Checksum status of the EEPROM loader of the hardware and firm-
ware configuration data
0x71 EEP_Controller_Mode
7, 0
R/W Mode of the EEPROM controller
0x72 EEP_Controller_Cmd
1-0
W Command for the EEPROM controller
Page 11 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011