STC5230_15 Datasheet, PDF (22/64 Pages) Connor-Winfield Corporation – Line Card Clock

STC5230
Synchronous Clock for SETS
Data Sheet
reference is qualified if it has no activity alarm and is
within the qualification range for more than the qualifi-
cation time. An activity alarm or frequency offset
beyond the disqualification range will disqualify the
reference. It may then be re-qualified if the activity
alarm is off and the reference is within the qualifica-
tion range for more than the qualification time.
The reference qualification status of each reference
may then be read from register Refs Qual.
When reversion (pre-emption) is enabled, the candi-
date reference will FbeunseclteicotendalimSmpeedciaifteiclyataisonthe
new active reference. When reversion is disabled, the
current active reference will not be pre-empted by any
candidate until it is disqualified.
The automatically selected active reference for each
DPLL may be read from the T(0/4) Auto Active Ref
registers.
Active Reference Selection
The T0 and T4 timing generators may be individually
operated in either manual or automatic input refer-
ence selection mode. The mode is selected via the
T(0/4) Control Mode registers.
Manual Reference Selection Mode
In manual reference selection mode, the user may
select the reference. This mode is selected via the
T(0/4) Control Mode registers. The reference is
selected by writing to the T(0/4) Manual Active Ref
registers.
Automatic Reference Selection Mode
In automatic reference selection mode, the device will
select one pre-qualified reference as the active refer-
ence. This mode is set via the T(0/4) Control Mode
registers.
The active reference is picked according to its indi-
cated priority in the reference priority table, registers
T(0/4) Priority Table. Each reference has one entry
in the table, which may be set to a value from 0 to 15.
‘0’ masks-out the reference, while 1 to 15 set the pri-
ority, where ‘1’ has the highest, and ‘15’ has the low-
est priority. The highest priority pre-qualified
reference then is a candidate to be the active refer-
ence. If multiple references share the same priority,
the one that has been qualified for the longest time
will be selected.
The active reference candidate will be promoted to be
the active reference immediately if no active refer-
ence exists. The operating mode will then enter syn-
chronized mode.
If the candidate reference is not the existing active
reference, it may or may not revert and pre-empt the
existing active reference. This is determined by either
enabling or disabling the “revertive” bit of the T(0/
4)_Control_Mode to “1” for revertive or to “0” for non-
revertive operation.
The pre-qualification scheme is described in the Ref-
erence Inputs Monitoring and Qualification sec-
tion.
Output Clocks
The clock output section includes 8 timing synthesiz-
ers and clock drivers. Generates 9 synchronized
clocks and T0_XSYNC_OUT. T0 timing generator
controls synthesizer G₀~G₆, G₈, and G₉. G₇ is con-
trolled by T4 timing generator as shown in Figure 5.
T0 DPLL
Synthesizer G₀
Synthesizer G₁
Synthesizer G₂
Synthesizer
F
LVCMOS
DRIVER
Synthesizer G₅
Synthesizer G₆
Synthesizer G₈
LVPECL
DRIVER
LVCMOS
DRIVER
LVCMOS
DRIVER
LVCMOS
DRIVER
LVCMOS
DRIVER
LVCMOS
DRIVER
CLK0
CLK1
CLK2
CLK3 (8kHz)
CLK4 (2kHz)
T0_XSYNC_OUT
CLK5
CLK6
CLK8
T4 DPLL
Synthesizer G₇
LVCMOS
DRIVER
CLK7
Figure 5: Output Clocks
STC5230 provides two modes to program the fre-
quency of CLK0~CLK8 (except CLK3 and CLK4):
Freq Pre Defined mode (default mode) and Freq User
Defined mode. CLK3 and CLK4 are frame pulse sig-
nal at fixed frequency of 8kHz and 2kHz.
Page 22 of 64 TM102 Rev: 3.0
© Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Date: September 14, 2011