AMD-762 Datasheet, PDF (99/122 Pages) Advanced Micro Devices – System Controller

24416C—December 2001
Preliminary Information
AMD-762™ System Controller Data Sheet
Table 34. Signal Descriptions (Continued)
Signal
WSC#
Type
Description
PCI Write Snoop Complete
WSC# is asserted to indicate that all of the snoop activity on the processor bus on behalf
of the last PCI-to-DRAM write transaction is complete. It indicates that an APIC interrupt
message can be sent. This signal is used only in configurations where an I/O APIC is
installed.
WSC# is driven asserted on the rising edge of PCICLK to indicate to the AMD-766™
B
peripheral bus controller that all probes due to PCI DMA (direct memory access) are
complete.
TS _{The AMD-768™ peripheral bus controller or AMD-766™ peripheral bus controller}
requests that the AMD-762™ system controller issue a fence command to its buffers by
placing a single PCICLK pulse on WSC#. The AMD-762 system controller then marks the
data currently in its buffers and waits for this data to reach processor-accessible
(coherent) space. When this data reaches processor-accessible space, the AMD-762
system controller responds by sending a two-clock pulse back to the AMD-768 or
AMD-766 peripheral bus controller. After this pulse is received, the AMD-766 peripheral
bus controller transmits the interrupt message over the interrupt message bus (IMB).
DDR DRAM Interface Signals
Note: DDR outputs are SSTL-2 compatible.
CS[7:0]#
DDR DIMM Chip Selects
CS[7:0]# function as chip-select signals for the DDR DRAMs.
O These signals are negated by RESET#. The memory controller asserts or negates these
signals relative to CLKOUT at the appropriate time in the memory access sequence. CS[7:0]
are driven a quarter of a cycle off from the CLKOUT rising edge to provide additional HOLD
time. See Chapter 2, “Functional Operation” starting on page 7 for more information.
DM[8:0]
DDR Data Masks/Data Strobes (for x4 DIMMs only)
DM[8:0] provides data masks for each byte during DDR writes to x8 and x16 DIMMs only.
For x4 DIMMs, these pins are used to provide the additional DQS pins required in x4
DIMM configurations. DM signals are not provided by x4 DIMMs. In the absence of the
DM function, partial writes result in full-line read-modify-write cycles with all bytes being
B ^{written active on the DIMM.}
These control signals are three-stated by RESET# and remain three-stated until driven by
the AMD-762 system controller during writes or by the DDR DRAM during reads. During
DDR writes to x8 and x16 DIMMs, the memory controller asserts or negates these signals
relative to the DQS[8:0] clock signals (described below). For x4 DIMMs, these pins
function as additional DQS strobe signals. See Chapter 2, “Functional Operation” starting
on page 7 for more information.
DQS[8:0]
DDR Data Strobes
DQS[8:0] are bidirectional data strobes between the memory devices and the memory
controller that are used to capture data. The data strobes (DQS signals) are source-
synchronous, which means that the DQS signals are driven by the device that is driving the
data. The “source-synchronous strobe” scheme is also referred to as the “clock-
B ^{forwarded” scheme. The AMD-762 system controller provides one DQS signal per byte of}
data for x8 and x16 DIMMs, or one DQS signal per nibble of x4 DIMMs. During a x4 DIMM
access, the DM pins provide the additional DQS strobe signals, which function the same as
the DQS strobe signals. An access to a x4 DIMM requires 18 data strobes (including ECC),
which are the DQS[8:0] and DM[8:0] pins combined. The AMD-762 system controller
implements a DQS scheme on the DDR interface that is similar to the clock-forwarded
scheme used on the AMD Athlon system bus interface.
Chapter 7
Signal Descriptions
87