AMD-762 Datasheet, PDF (25/122 Pages) Advanced Micro Devices – System Controller

24416C—December 2001
CLKOUTH
MAx[14:0]
RASx#
CASx#
CS[7:0]#
CS0
Preliminary Information
AMD-762™ System Controller Data Sheet
CS1
Figure 6. DRAM Refresh Timing
2.2.2
DDR Data Strobes
Unlike single data rate SDRAMs, Double Data Rate (DDR)
does not latch data on the rising edge of the memory clock.
Instead, DDR devices specify bidirectional data strobes (DQS
pins) between the system memory controller and the DDR
memories that are used to capture data. The data strobes are
source-synchronous, which means that the DQS signals are
driven by the device that is currently driving the data bus. The
AMD-762 system controller provides one DQS pin per byte
when using x8 and x16 DIMMs, or one per nibble when using
x4 DIMMs. The Data Mask (DM) pins provide the additional
DQS strobe function when accessing a x4 DIMM. The DM pins
no longer provide a mask function when performing a write
access to a x4 DIMM. Therefore, a read-modify-write cycle
occurs for partial write accesses (“partial” implying an
incomplete quadword of data). In the case of writes to memory,
the AMD-762 system controller must drive DQS such that each
edge is centered in the write-data valid window to allow the
DDR DRAMs to capture the data on each edge of the strobe.
For memory reads, the devices drive the DQS pins edge-aligned
with the memory clock, and the AMD-762 system controller
must center the DQS with the incoming data. Delaying the DQS
accordingly for each byte or nibble is required. Because this
t i m i n g i s ve ry t i g h t , t h e A M D -7 6 2 s y s t e m c o n t ro l l e r
implements Programmable Delay Lines (PDLs) to accomplish
this centering of DQS with the data. A separate PDL is
implemented for each DQS pin.
Chapter 2
Functional Operation
13