AMD-762 Datasheet, PDF (22/122 Pages) Advanced Micro Devices – System Controller

Preliminary Information
AMD-762™ System Controller Data Sheet
24416C—December 2001
2.2
Memory Interface
The AMD-762 memory controller arbitrates and optimizes
incoming memory requests, handles ECC and Graphics
Address Remapping Table (GART), and controls up to four
double-data-rate (DDR) SDRAM DIMMs.
The AMD-762 system controller memory interface is designed
to support registered DDR DIMMs. Up to four registered
DIMMs can be supported by the AMD-762 system controller.
The AMD-762 system controller supports 64-Mbit, 128-Mbit,
256-Mbit, and 512-Mbit DDR devices. Device widths of x4, x8,
and x16 are supported. Mixed banks are supported, meaning
that a x8 DIMM can coexist with x4 and x16, etc.
Refer to Table 1 on page 11 for the total memory sizes for
various registered DIMM configurations. A total of 4 Gbytes is
supported.
DDR timing parameters are programmable via the AMD-762
system controller’s memory controller configuration registers,
allowing support of different DIMM configurations and
loading. Refresh is also programmable, with support of various
refresh rates as well as the ability to queue up to four
outstanding refreshes. Clock pairs can also be selectively
disabled to unpopulated DIMM slots via configuration register
bits in the memory controller.
The memory controller supports up to four open pages in the
active chip select. All pages in a chip select are closed when an
access to another chip select is detected. Memory page
operation can be further optimized by programming the
number of idle cycles to a bank before the bank is
automatically precharged.
10
Functional Operation
Chapter 2