AMD-762 Datasheet, PDF (69/122 Pages) Advanced Micro Devices – System Controller

24416C—December 2001
Preliminary Information
AMD-762™ System Controller Data Sheet
CLKOUTH[5:0]
CLKOUTL[5:0]#
t_CKlo
t_CKhi
Figure 15. DDR Clock Specifications
Table 21 shows the AMD-762 system controller preliminary
timing information.
Table 21. AMD-762™ System Controller Preliminary DDR Timing Information*
Symbol
Parameter Description
Min
Max Unit Figure
V_IL (AC) AC Input Low Voltage
V_REF – 0.35 V
V_IH (AC) AC Input High Voltage
V_{REF + 0.35}
V
t_ADsu
ADDR/CMD Setup to CK
7.5
8.5
ns
t_ADhld
ADDR/CMD Hold from CK
2.5
3.6
ns
t_DQsu
DQ/DM Setup to DQS
2.4
2.5
ns
t_DQhld
t_WPREsu
t_WPREhld
DQ/DM Hold from DQS
Write Preamble Setup
Write Preamble Hold
2.4
2.6
ns
2.8
3.4
ns
Figure 17
on page 59
5.1
5.8
ns
t_WpostA Write Postamble
4.5
5.0
ns
t_DSsu
DQS Falling Edge to Next CK Rising Edge
5.2
5.6
ns
t_DQSdly Write Command to First DQS Latching Transition
9.0
9.9
ns
Notes:
* _{This table contains preliminary information, which is subject to change. Timing reference load (applied to all chip-level outputs) used for all}
information contained herein is a 30-pF capacitance. A CAS latency of 2.5 is used unless otherwise indicated.
DDR Write Timing
Figure 16 on page 58 shows a DDR interface output block
diagram. Figure 17 on page 59 shows basic AC timing for DDR
write cycles.
Note: All information shown under DDR Write Timing is preliminary.
Chapter 4
Electrical Data
57