AMD-762 Datasheet, PDF (15/122 Pages) Advanced Micro Devices – System Controller

24416C—December 2001
Preliminary Information
AMD-762™ System Controller Data Sheet
n BIOS-configurable memory-timing parameters and
configuration parameters
n 2.5-V memory interface operation with no external buffers
or PLLs
n Concurrent DRAM writeback and read-around-write
n Burst read and write transactions
n Decoupled and burst DRAM refresh with staggered CS
timing
n Provides the following refresh options:
• Programmable refresh rate
• CAS-before-RAS
• Populated banks only
• Automatic refresh of idle slots—improves bus availability
for memory access by the processor or system
1.3 PCI Bus Controller
The PCI bus controller has the following features:
n Compliance with PCI Local Bus Specification, Revision 2.2.
n Supports up to seven PCI bus masters plus the AMD-766
peripheral bus controller when operating in 33-MHz-only mode,
or up to two PCI bus masters and the AMD-768 peripheral bus
controller when operating in 66/33-MHz PCI mode.
n 64-bit interface, compatible with 3.3-V and 5-V PCI I/O
n Synchronous PCI bus operation up to 66 MHz
n PCI-initiator peer concurrency
n Automatic processor-to-PCI burst cycle detection
n Zero wait-state PCI initiator and target burst transfers
n Enhanced PCI command optimization, such as Memory
Read Line (MRL), Memory Read Multiple (MRM), and
Memory-Write-and-Invalidate (MWI)
Chapter 1
Features
3