AMD-762 Datasheet, PDF (19/122 Pages) Advanced Micro Devices – System Controller

24416C—December 2001
Preliminary Information
AMD-762™ System Controller Data Sheet
2 Functional Operation
2.1
2.1.1
This section describes the functional operation of the
AMD-762™ system controller.
Processor Interface
The two AMD Athlon processor system buses are high-
performance, out-of-order, split-transaction buses, each
capable of transferring one processor command and one probe
response, one chip-set response and one probe request, and one
data packet simultaneously. Data and command packets are
transferred as packets of two, four, or eight datums on each
edge of the 100-MHz or 133-MHz clock.
Out of Order, Split Transaction
The split transaction buses separate the transfer of the
command and the associated data into different transactions
on different buses. Data may be returned in a different order
than it was requested, subject to ordering rules.
A read transaction consists of a Read command sent from the
processor to the memory system over the SADDOUT bus. When
the memory system is ready to return data, a ReadData
command is sent to the processor over the SADDIN bus to alert
the processor that data is coming and identify the associated
data request. The data is sent to the processor over the SDATA
bus a programmable number of clocks later. Similarly, a write
transaction is sent to the chipset over the SADDOUT bus, the
chipset requests the associated write data over the SADDIN
bus, and the data is transferred over the SDATA bus a
programmable number of clocks later. Probes and probe
responses are piggybacked with the other commands on the
SADDIN and SADDOUT bus.
The split transaction scheme provides a high degree of
parallelism between the various buses and facilitates pipeline
flow or memory requests and responses.
Chapter 2
Functional Operation
7