AMD-762 Datasheet, PDF (44/122 Pages) Advanced Micro Devices – System Controller

Preliminary Information
AMD-762™ System Controller Data Sheet
24416C—December 2001
6. The AMD-762 system controller issues a Stop Grant special
cycle on the PCI bus.
7. The Southbridge asserts DCSTOP#. The AMD-762 system
controller follows the normal DCSTOP# protocol as
described in “S1 Sequence” on page 28, including gating
most of the internal clocks off. The DDR output clocks
(CLKOUT[5:0], CLKOUT[5:0]#) continue running for an
additional six clock periods from the assertion of RESET#.
This action is required because the DIMM reset signal on
registered DIMMs is connected to the AMD-762 system
controller RESET# pin, and the DIMM clocks must be
running while the DIMM reset is first asserted.
8. The Southbridge asserts PCIRST# (RESET# on the
AMD-762 system controller). The AMD-762 system
controller continues driving the CKE pins Low, and gates off
the I/O pads to prevent driving 1s to the unpowered I/O ring
and to inhibit floating inputs from the unpowered I/O rings
to the powered core logic. The input clock pins (SYSCLK,
AGPCLK, and PCICLK) are also gated off because these
input pins are floating when the motherboard’s 3.3 Vdc is
powered off. The two STR bits in the DRAM Mode/Status
register (Dev 0:F0:0x58) are cleared to 0s. The state of all
other memory controller configuration register bits is
preserved.
9. The Southbridge signals the power supply (deasserts
PWRON#) to shut down all but the 5-Vdc and 2.5-Vdc
voltages. The motherboard clock generator chip shuts down,
therefore the input clocks (SYSCLK, AGPCLK, and
PCICLK) float.
32
Functional Operation
Chapter 2