AMD-762 Datasheet, PDF (42/122 Pages) Advanced Micro Devices – System Controller

Preliminary Information
AMD-762™ System Controller Data Sheet
24416C—December 2001
STPCLK#
CPU BUS
PCI BUS
Stop Grant Special Cycle
2
3
4
Stop Grant Special Cycle
6
DCSTOP#
7
CKEA
CKEB
CLKOUTH[n]
Running Full Speed
8
CLKOUTL[n] Running Full Speed
MAA[14:0]
MAB[14:0]
RASn#/CASn#/WEn#
DQS[8:0]
Drive n by the A M D -762™
System Controller during
DRAM Write Cycles.
5
S1 Sleep State
Enter Self-Refresh
Note: Circled numbers correspond to “S1 Sequence” on page 28.
240 µs
Figure 10. Power On Suspend System Timing Diagram Example
This state is exited when the DCSTOP# signal is deasserted by
the Southbridge, followed by a deassertion of STPCLK#. This
action causes the AMD-762 system controller to enable the
clock trees and prepare to reconnect the processor. The
processors assert their respective PROCRDY signal, which
causes the AMD-762 system controller to exit self-refresh and
reconnect the AMD Athlon processor system buses. The
A M D -7 6 2 s y s t e m c o n t ro l l e r re t a i n s t h e s t a t e o f a l l
configuration registers during the S1 state.
2.6.5
Suspend to RAM (S3)
The S3 state is similar to S1. However, power is removed from
most of the motherboard except the A MD-762 system
controller, DRAM, and a portion of the Southbridge. S3 is the
30
Functional Operation
Chapter 2