AMD-762 Datasheet, PDF (57/122 Pages) Advanced Micro Devices – System Controller

24416C—December 2001
Preliminary Information
AMD-762™ System Controller Data Sheet
3.4
options for PLL bypass mode as listed in Table 6 below.
Because the AMD-762 system controller internal logic normally
uses clocks that are 2x the SYSCLK input and 2x/4x the
AGPCLK input, the PLL bypass mode requires that either 2x or
4x clocks be driven in this mode, but they can be driven at a
much lower frequency for test purposes. Note that when
operating in this mode, the minimum clock frequency most
likely will be dictated by the surrounding logic, such as the
DDR interface.
Table 6. Clocking Options in PLL Bypass Test Mode
Mode
Normal
C/BE[1]#
0
AGP-4x Testing 1
SYSCLK
2x
2x
AGPCLK
Comments
PLLs bypassed, drives a 2x clock
2x to internal divider, and resulting
1x clock to internal logic.
Same as above, except allows 4x
4x clock to accommodate 4x AGP
testing.
The PLL reset function can be invoked by asserting a Low on
the PCI IRDY# pin This procedure provides a synchronous
reset for the clocking, but probably is not required when using
this test mode for motherboard debug.
Note: AD[29] must be pulled Low when entering PLL bypass test
mode to enable the PLL reset function capability.
Clock Output Test Mode
The clock output test mode provides external visibility of the
two PLLs used to generate the clocks for the processor/memory
and AGP clock domains. In this test mode, the PLLs are
running, and the output clocks are driven to GNT[6:5]# pins.
System designers that intend to make use of this test feature
should provide 0-ohm resistors on these pins to isolate the PCI
peripherals when observing the clocks.
This test mode is entered by the Low assertion of the TEST#
pin while pulling the PCI bus PAR pin Low. Additional
pinstraps are then used to select the various clock outputs as
illustrated in Table 7 on page 46.
Chapter 3
Test
45