AMD-762 Datasheet, PDF (102/122 Pages) Advanced Micro Devices – System Controller

Preliminary Information
AMD-762™ System Controller Data Sheet
24416C—December 2001
Table 34. Signal Descriptions (Continued)
Signal
A_DEVSEL#
A_FRAME#
A_GNT#
A_IRDY#
A_PAR
A_REQ#
A_SERR#
A_STOP#
A_TRDY#
Type
Description
APCI Device Select
The AMD-762™ system controller asserts this pin when an external bus master drives a
B _{valid address within the memory region of the AMD-762 system controller. The AMD-762}
STS ^{system controller responds only to memory cycles. This pin is sampled by the AMD-762}
system controller when the CPU accesses a PCI target.
A_DEVSEL# is not used during AGP transfers.
APCI Cycle Frame
B
The A_FRAME# pin is asserted by the AMD-762 system controller to indicate the
beginning of a bus transaction. A_FRAME# is sampled by the AMD-762 APCI target
STS _{controller when an external bus master is performing a transaction on the PCI bus.}
A_FRAME# is not used during AGP transfers.
AGP/APCI Bus Grant
As the AGP bus arbiter, the AMD-762 system controller asserts A_GNT# in response to
O
A_REQ# from the initiator (graphics controller) to indicate to the initiator that it has been
granted control of the bus. At the same time, the system controller provides status
TS _{information on status signals ST[2:0] to indicate to the initiator whether it is to supply data}
or receive data in response to a previously queued request.
A_GNT# is asserted in response to an A_REQ#. A reset forces A_GNT# to be negated.
AGP/APCI Initiator Ready
B _{The AMD-762 system controller asserts this signal during APCI transactions to indicate that}
STS write data is valid or it is ready to receive read data. It is sampled by the AMD-762 system
controller during transactions by the AGP master.
APCI Bus Parity
B _{PAR is used to generate and check for even parity across the AAD[31:00] and A_C/BE[3:]#}
TS ^{pins. The AMD-762 system controller generates but does not check parity.}
A_PAR# is not used during AGP transfers.
AGP/APCI Bus Request
I ^{As the bus arbiter, the AMD-762 system controller monitors A_REQ# to determine if the}
graphics controller requests access to the AGP bus. If A_REQ# is sampled asserted, the
arbiter asserts A_GNT# as soon as the bus is available.
APCI System Error
I
A_SERR# is not used during AGP transfers. An assertion on the A_SERR# pin during APCI
transfers can be forwarded to the PCI SERR# pin when enabled in AMD-762 configuration
registers.
APCI Bus Stop
B ^{The A_STOP# signal is asserted by the AMD-762 APCI target logic to initiate a disconnect}
STS
by the AGP master. As a master, the AMD-762 system controller stops the current transfer
when it samples the A_STOP# signal asserted.
A_STOP# is not used during AGP transfers.
AGP/APCI Target Ready
B The A_TRDY# signal is asserted by the AMD-762 system controller during accesses by an
STS
external bus master when read data is valid or when the target logic is ready to receive
write data. This signal is sampled by the AMD-762 AGP master logic when the AMD-762
system controller is accessing an external APCI target.
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Signal Descriptions
Chapter 7