AMD-762 Datasheet, PDF (43/122 Pages) Advanced Micro Devices – System Controller

24416C—December 2001
Preliminary Information
AMD-762™ System Controller Data Sheet
S3 Sequence
lowest power sleep state, and allows very fast resume because
system context is stored in memory instead of on disk.
The S3 state is entered similarly to S1 with a Stop Grant special
cycle and DCSTOP#. After entering S3 state with DCSTOP#
assertion, the Southbridge asserts the RESET# signal, which
causes the AMD-762 system controller to gate off its I/O rings
to accommodate the voltages being removed from the
AMD Athlon processor system bus, PCI bus, and AGP bus. The
AMD-762 system controller core remains powered (2.5 Vdc) as
does the DDR I/O interface and the DDR DIMMs, to allow the
memory to remain in self-refresh mode with the CKE pins
driven Low. The sequence of operation for entering the S3 state
is listed below. Figure 11 on page 33 shows a suspend to RAM
system timing diagram example.
1. As with the S1 state, the device drivers are called to place
all devices into the D3 device state, which prevents them
from trying to master on the bus they reside (or access
system memory).
2. The ACPI driver (or BIOS under APM) writes to the
appropriate registers in the Southbridge to initiate the
hardware sequence into the S3 state. In response to this
write, the Southbridge asserts STPCLK# to the AMD Athlon
processors. Once STPCLK# has been asserted, the power
management state machine in the Southbridge waits for a
Stop Grant special cycle on the PCI bus before completing
the transition into the S3 state.
3. The CPUs recognize that STPCLK# has been asserted,
flushes internal buffers, and generates a Stop Grant cycle
on the AMD Athlon processor system bus.
4. After detecting both Stop Grant special cycles on the
processor buses, the AMD-762 system controller flushes all
internal queues including outstanding probes, then
deasserts the CONNECT pins. The CPUs respond by
deasserting their respective PROCRDY pins.
5. When the disconnect is complete, the AMD-762 system
controller executes a self-refresh command to the DDR
SDRAM and waits for it to complete (this action is
accomplished by issuing an auto-refresh command and
driving the CKE signals Low to the DRAM).
Chapter 2
Functional Operation
31