AMD-762 Datasheet, PDF (68/122 Pages) Advanced Micro Devices – System Controller

Preliminary Information
AMD-762™ System Controller Data Sheet
24416C—December 2001
SYSCLK
1.15 V
AGPCLK
0.4 (VDD_PCI)
Figure 14.
t_Skew
t_Skew
Clock Skew Requirements
4.5.2
DDR Interface Timing
Table 19 and Table 20 show the DDR SDRAM interface
timings. Figure 15 on page 57 shows DDR clock specifications.
The AMD-762 system controller’s DDR DRAM interface complies
to JEDEC specifications for 100/133-MHz device timing.
Table 19. DDR Clock Switching Characteristics for 100-MHz DDR Operation
Symbol
t₁
t₂
Parameter Description
Frequency
CLKOUTH/L[5:0] High Time
CLKOUTH/L[5:0] Low Time
CLKOUTH/L[5:0] Fall Time
Preliminary Data
Min
4.75 ns
Max
100 MHz
4.75 ns
0.86 ns
1.30 ns
CLKOUTH/L[5:0] Rise Time
0.86 ns
1.30 ns
CLKOUTH/L[5:0] Period Stability
± 2%
CLKOUTH/L[5:0] Skew
0
0.12 ns
*_{This table contains preliminary information, which is subject to change.}
Figure
15
15
Table 20. DDR Clock Switching Characteristics for 133-MHz DDR Operation
Symbol
t₁
t₂
Parameter Description
Frequency
CLKOUTH/L[5:0] High Time
CLKOUTH/L[5:0] Low Time
CLKOUTH/L[5:0] Fall Time
Preliminary Data
Min
3.625 ns
Max
133 MHz
3.625 ns
0.86 ns
1.30 ns
CLKOUTH/L[5:0] Rise Time
0.86 ns
1.30 ns
CLKOUTH/L[5:0] Period Stability
± 2%
CLKOUTH/L[5:0] Skew
0
0.12 ns
*_{This table contains preliminary information, which is subject to change.}
Figure
15
15
Comments
Drive strength:
P = 3, N = 2;
P_SLEW = 5, N_SLEW = 5
Relative to all other
CLKOUTH/L pairs
Comments
Drive strength:
P = 3, N = 2;
P_SLEW = 5, N_SLEW = 5
Relative to all other
CLKOUTH/L pairs
56
Electrical Data
Chapter 4